Implementing Different Adder Structures in Verilog
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Updated
Sep 3, 2019 - Verilog
Implementing Different Adder Structures in Verilog
Solution to COA LAB Assgn, IIT Kharagpur
Extremely basic CortexM0 SoC based on ARM DesignStart Eval
Repository to store all design and testbench files for Senior Design
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
Dosage is a 20 bit risc cpu, based on Harvard architecrure aimed for educational purposes.
This project is being developed as part of a Master's degree research sponsored by Brazil's CNPQ. It's goal is to design a hardware architecture to accelerate the AV1 arithmetic encoder.
Simple queue management system
Design MMU for socfpga-linux 4.11. Test with Altera DE2-115.
Practices related to the fundamental level of the programming language Verilog.
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
Brilliantly Radical Artificially Intelligent Neural Machine
Hardware designs modelled with verilog
Student-project
A MIPS processor in VHDL for FPGA and ASIC
Complex Programmable Logic Device (CPLD) Guide
Verilog code for my paper that proposes a secure-AES algorithm with support for various FPGA boards.
RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor
A nearly holistic CPU with MIPS architecture implementing 50+ instructions together with cache and TLB.
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