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A toolbox for automating some of the more tedious refactoring tasks comming with common HDL languages (VHDL/Verilog). Including among others: entity to instance conversion and entity cross language conversion.
HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project
This project automates process of creating a PYNQ Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.