Systolic array-based Matrix Profile Computation implemented in Vitis™ HLS for Xilinx FPGAs.
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Updated
Sep 7, 2021 - C++
Systolic array-based Matrix Profile Computation implemented in Vitis™ HLS for Xilinx FPGAs.
A tool to generate optimized hardware files for univariate functions.
AES algorithm for High Level Synthesis
m3u8player is a tool on top of dart to play m3u8 files with HLS support on mobile applications using chewie controller and for extra bonus it can also play mp4 video files
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs
Building HLS accelerated applications for cloud FPGAs
This is a watch party video streaming app
Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)
A simple C++ broadcasting library fro audio coming from custom sources (e.g. generated by a program).
High level synthesis projects and practices
High Level synthesis of data transfer in Vivado, Vivado HLS
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