Wishbone controlled I2C controllers
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Updated
Feb 22, 2024 - Verilog
Wishbone controlled I2C controllers
Verilog module for I2C Master, up to 16 bit sub addr, 7bit slave address, and multiple byte read/write capable
Custom i2c modules and ip cores
openMSP430 project ported to Terasic DE0 and DE0CV. (I2C master core and basic UART included)
The several codes i have seen so far uses sequential execution of the scl and sda and therefore sda changes when scl is at the edge.But in my code the sda changes only when scl is exactly at zero(Like the actual waveform of the I2C protocol)
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