fibonacci number calculator written in Verilog-HDL
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Updated
Feb 23, 2017 - Verilog
fibonacci number calculator written in Verilog-HDL
Verilog codes developed as a part of COA lab course
🔮 A 16-bit MIPS Processor Implementation in Verilog HDL
Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
Embedded Systems Lab Work
This repo consists of the iverilog implementation of a Parallel Prefix adder - 8bit (I/P - O/P). This was done as a part of a project Under UE19CS206 - Digital Design and Computer Organization Laboratory Course at PES University.
Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim
16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.
💎 A 32-bit ARM Processor Implementation in Verilog HDL
🛠 A SDRAM controller in Verilog HDL
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