A cross platform C99 library to get cpu features at runtime.
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Updated
Jun 18, 2024 - C++
A cross platform C99 library to get cpu features at runtime.
A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).
A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical path, as described by MICRO 2022 paper by Bera et al. (https://arxiv.org/pdf/2209.00188.pdf)
Achieve peak performance on x86 CPUs and NVIDIA GPUs
Kite: Architecture Simulator for RISC-V Instruction Set
Development repository for Fetch Directed Instruction Prefetching (FDP) in gem5
DSCP is a dynamic secure cache partitioning implementation on gem5. The code includes a ScatterCache (USENIX SECURITY'19) variant and it is partially available to reproduce set partitioning.
A runahead execution CPU model in the gem5 simulator - feat. delayed exit experiments
[2009 – 2012] MDSP: functional simulation of a Multimedia Digital Signal Processor
A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program.
CPU Pipeline Visualization Tool
Class project for ECE721: Advanced Microarchitecture. This project involves implementing a renamer class that uses AMT, RMT, Active List, Free List, and Physical Register File.
Implements a BDP (Branch difference predictor) based on the paper by Timothy H Heil, Zak Smith and JE Smith - "Improving branch predictors by correlating on data values"
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