NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
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Updated
Jul 7, 2020 - SystemVerilog
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
A simplified MIPS machine simulator using SystemVerilog, developed with three different micro-architectures: single-cycle, multi-cycle and pipelined.
Implementation of a mips-based processor architecture using SystemVerilog and VHDL
MIPS architecure processor on Intel FPGA.
MIPS written in System Verilog
Mips Single-Cycle, Computer Architecture course, University of Tehran
Single Cycle 32 bit MIPS
An implementation of Mips processor - My Computer Architecture course final project
An Implementation of MIPS processor with single/multi-cycle architecture using SystemVerilog language.
BP-1 8 bit Microprocessor written for ECEN 2350
A complete hardware description of a non-pipeline MIPS processor in SystemVerilog that can execute integer assembly code implemented on the Altera DE2-115 FPGA.
A synthesizable simplified MIPS written in System Verilog
Mips Multi-Cycle, Computer Architecture course, University of Tehran
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