DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA
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Updated
Jul 30, 2022 - SystemVerilog
DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA
Basic Stopwatch Design using Terasic DE-10 Standard FPGA
Computer Architecture Lab - Assignments - Fall 2023
Repository of homeworks and projects of the verification class from Bootcamp Pre-Silicon at ITESO with INTEL
Scrolling Display Implemented With Digital Design Concepts on De1-SoC
Pipeline Processor based on RISC-V, implemented forwarding and hazard detection units
This project was a nice idea I had to build a digital logic clock on the DE1-SOC FPGA, while practicing System-verilog, Asynchronous design, and advanced debugging techniques
UART Receiver and Transmitter using Terasic DE-10 Standard FPGA
FPGA stuff
Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA
A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL
CAPIPrecis a Coherent Accelerator Processor Interface (CAPI) Abstract Layer
SublimeText3 bits for Quartus, ModelSim, and VUnit Integration mirror of https://phabricator.kairohm.dev/diffusion/10/
simple read/write pcap tasks for SystemVerilog test
Single-Cycle RISC-V Processor in systemverylog
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