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opensta

Here are 2 public repositories matching this topic...

Pa1mantri / VSD_Hardware_Design

Pre and Post Synthesis Simulation of a Design VSDMemSOC

riscv gtkwave verilog-hdl yosys iverilog digital-design opensta

Updated May 5, 2024
Verilog

Pa1mantri / VSDMemSOC

VSDMemSOC Implementation flow:: RTL2GDSII

macros riscv yosys gdsii physical-design openroad opensta openlane-flow sram-macro

Updated Mar 1, 2024
Verilog

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