NTUEE Switching Circuits and Logic Design 21Fall Quartus Lab

Simple test for interfacing FPGA and SoC on a de10 nano board

Experiments for "Digital Systems Design Lab".

Project file made on Quartus in Verilog. With components: Ripple Carry, Full Adder and Half Adder

A 16 bit processor, following the RISC architecture. Made with Quartus and VHDL.

FPGA Cripto Algorithm Hummingbird

Структурная и функциональная организация ЭВМ (СиФОЭВМ) - л. р.

Verilog Implementation of the LC-3 Processor. DA CS 603

📚Repositório da Disciplina INE5406 - Sistemas Digitais