risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 109 public repositories matching this topic...
A secure embedded operating system for microcontrollers
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May 29, 2024 - Rust
Let's write an OS which can run on RISC-V in Rust from scratch!
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May 10, 2024 - Rust
A fully compliant RISC-V computer made inside the game Terraria
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Dec 10, 2023 - Rust
Hardware abstract layer (HAL) `embedded-hal` for RISC-V microcontroller GD32VF103 in Rust. Contributions welcomed!
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Dec 28, 2021 - Rust
A toy operating system written in Rust on RISC V(rv32im)
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Mar 30, 2023 - Rust
Mirror; Work-in-progress software-rendering Vulkan implementation
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Apr 1, 2020 - Rust
A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V
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Dec 21, 2021 - Rust
Microkernel and userspace written in Rust exploring modern ideas
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May 27, 2024 - Rust
R3-OS — Experimental static (μITRON-esque) RTOS for deeply embedded systems, testing the limit of Rust's compile-time evaluation and generics
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Apr 22, 2023 - Rust