ytliu74 / RISCV_Verilog Star 13 Code Issues Pull requests RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA. verilog risc-v sjtu Updated Jun 3, 2023 Verilog
qinchuanhui / SJTU-CS-project Star 2 Code Issues Pull requests The projects of some undergraduate courses of CSE, SJTU sjtu Updated Feb 15, 2021 Verilog
forestLoop / Learning-EI332 Star 1 Code Issues Pull requests My FPGA designs in Course EI332 (Computer Organization). fpga verilog sjtu Updated Jun 15, 2019 Verilog
ycq091044 / awesome-scs Star 2 Code Issues Pull requests 上海交通大学网安学院本科编程作业参考 information-security sjtu Updated Jul 16, 2018 Verilog