This repository aims to automatically generates source files for HDL
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Updated
Jun 5, 2019 - Python
This repository aims to automatically generates source files for HDL
Example of Python and PyTest powered workflow for a HDL simulation
Segundo proyecto para el curso de Arquitectura de Computadores. La idea es hacer un ASIP (Application Specific Set Processor) que genere interpolación de imagen por medio de un compilador, código en ensamblador, un procesador pipeline y scripts en alto nivel.
Templates generator: make Verilog/SystemVerilog module template by parameters and ports list
Spice to Verilog Converter
Control and Status Register map generator for HDL projects
A functional verification framework for digital hardware.
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