UVM Book Examples - A Practical Guide to Adopting the Universal Verification Methodology (UVM) Second Edition by Kathleen Meade and Sharon Rosenberg
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Updated
May 14, 2024 - Verilog
UVM Book Examples - A Practical Guide to Adopting the Universal Verification Methodology (UVM) Second Edition by Kathleen Meade and Sharon Rosenberg
A simple SHA-256 implementation in VHDL and Verilog, simulated using a basic UVM testbench.
Designing means to communicate as an SPI master, being a part of AXI interface
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
my UVM training projects
INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
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