This repo contains the EEL2020 course project, which was instructed to be made in hindi.
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Updated
Jul 2, 2024 - HTML
This repo contains the EEL2020 course project, which was instructed to be made in hindi.
Snake game using Verilog on Spartan®-6 FPGA
4bit_CLA_Adder_7seg in Xilinx Vivado Verilog
CSE460 - VLSI Design
A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)
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