vhdl
Here are 38 public repositories matching this topic...
FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS
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Mar 1, 2021 - Tcl
fhlow (fast handling of a lot of work), a build and working environment that speeds up the development of and structures FPGA design projects
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Sep 24, 2019 - Tcl
A small FPGA and APSoC project of different implementations for testing byte-by-byte a serial flash. Refresh of fpga-serial-mem-tester-1 and -2.
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Mar 4, 2023 - Tcl
A small FPGA and APSoC project of different implementations for testing Measurement and Activity Events of a SPI accelerometer. Refresh of fpga-serial-acl-tester-1 and -2.
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Apr 14, 2024 - Tcl
Collection of FPGA modules for video capture and processing.
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Feb 3, 2023 - Tcl
A test IP that receives a packet from the NoC, increments its the payload, and sends the packet back to the source
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Jul 25, 2020 - Tcl
A FPGA project using a Pynq-Z2 for audio (I2S AXI) and video (HDMI) pipelining
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Jun 11, 2021 - Tcl
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Jan 17, 2022 - Tcl
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Jan 27, 2020 - Tcl
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