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93 public repositories
matching this topic...
Bilgisayar Organizasyonu Verilog Projeleri
Updated
Jan 12, 2018
Verilog
Verilog module to understand the use of FPGA 4x4 hex matrix keypad and display the outputs in multiplexed 7 segment display.
Updated
Oct 20, 2023
Verilog
A BCD counter that counts from 0 to 9999 is created and is verified on the multiplexed 7-segment display on the Spartan 6 FPGA.
Updated
Oct 24, 2023
Verilog
MOD 12 counter counts up to 11 and repeats. Implemented in FPGA and outputs are displayed using multiplexed 7 segment display.
Updated
Oct 9, 2023
Verilog
An arithmetic and logic unit (ALU) is created and tested and simulated with several inputs using a Verilog testbench.
Updated
Oct 10, 2023
Verilog
Digital Circuit Design projects implemented using VHDL, Verilog
Updated
May 22, 2024
Verilog
A study of soft-core CPUs for use with FPGA designs
Updated
Jan 11, 2024
Verilog
Verilog is a hardware description language. This repo is basically a learning journey of verilog
Updated
Aug 21, 2023
Verilog
A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.
Updated
May 24, 2024
Verilog
DLX processor from RTL down to physical design
Updated
Sep 26, 2023
Verilog
A tiny Open POWER ISA softcore written in VHDL 2008
Updated
May 9, 2024
Verilog
Programmable Logic Embedded System Design Project Repository
Updated
Nov 23, 2020
Verilog
Basic digital designs developed with Verilog and VHDL.
Updated
Mar 9, 2024
Verilog
This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.
Updated
May 16, 2024
Verilog
Updated
Aug 1, 2023
Verilog
Programmable Logic Embedded System Design Homework Repository
Updated
Nov 24, 2020
Verilog
A simple 4 bit counter using clock divider is created and implemented using Spartan 6 FPGA. Outputs are displayed in LEDs
Updated
Oct 7, 2023
Verilog
Verilog module to understand the use of FPGA dip switches and display the outputs in multiplexed 7 segment display.
Updated
Oct 16, 2023
Verilog
Updated
Jan 3, 2021
Verilog
A simple SHA-256 implementation in VHDL and Verilog, simulated using a basic UVM testbench.
Updated
Oct 23, 2022
Verilog
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