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aryan-programmer / axi_stream_array_sum_microblaze

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A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.

embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado microblaze axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls
  • Updated Dec 3, 2023
  • C

gubbriaco / FPGA-VHDL-filtering-circuit-grayscale-images

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Star 1

A project that involves the hardware design (VHDL) of a circuit on FPGA that performs the filtering of an image through an isotropic filter. The circuit is also tested and validated (both from the point of view of the error and from the point of view of the quality of the filtering) through procedures described in MATLAB.

fpga matlab vhdl image-processing image-manipulation xilinx vivado filtering pynq-z2
  • Updated Aug 23, 2023
  • C

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