Baremetal C application that displays encoder values on a serial interface, starting from a Vivado block design and transitioning to a Vitis application.
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Updated
Jun 11, 2024 - C
Baremetal C application that displays encoder values on a serial interface, starting from a Vivado block design and transitioning to a Vitis application.
This is my sandbox for experimenting with the features offered by the AMD (Xilinx) FreeRTOS port. The main platform used is the Digilent Zybo-z7-20. The implemented system is quite simple, comprising a range of GPIO features (LEDs, buttons, switches, and test outputs for monitoring) and two UART communication channels.
CyDAQ DSP Platform Firmware and Software Redesign - Iowa State University Senior Design May 2023 Group 47 - Blake Fisher, Cole Langner, Corbin Kems, Jens Rasmussen, Long Zeng, Wyatt Duberstein, Yohan Bopearatchy
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
A project that involves the hardware design (VHDL) of a circuit on FPGA that performs the filtering of an image through an isotropic filter. The circuit is also tested and validated (both from the point of view of the error and from the point of view of the quality of the filtering) through procedures described in MATLAB.
Konkuk Univ. 3rd grade, Term-project from Embedded Computing class
This project implement a synchronous sequential circuit which detects two different 4-bit sequences, A and B.
This repository is for an exercise in the university.
Learn how to get started with BeetleboxCI and Vivado following this simple tutorial designing a multiplexer
2110363 Hardware Synthesis Lab I (2022/1) - Term Project
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