Lab work for VLSI for computer science. It formalizes the notion of hierarchical design of Integrated Circuits and abstracts the notion of design of integrated circuits.
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Updated
Nov 19, 2020 - Verilog
Lab work for VLSI for computer science. It formalizes the notion of hierarchical design of Integrated Circuits and abstracts the notion of design of integrated circuits.
Approximate multipliers of 8bit and 16bit
Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier
All the projects and assignments done as part of VLSI course.
Library of approximate arithmetic circuits
Standard Cell Library based Memory Compiler using FF/Latch cells
A Standalone Structural Verilog Parser
A High-performance Timing Analysis Tool for VLSI Systems
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