vlsi-design

Here are 35 public repositories matching this topic...

dhwanish-3 / Verilog-Programming-Logic-Design-Lab

Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator

verilog modelsim verilog-hdl logic-design intel-fpga vlsi-design verilog-code

Updated Feb 21, 2024
Verilog

1rsh / EC39004

Star

This repository contains code files for VLSI Laboratory - EC39004, conducted in Spring 2024 at IIT Kharagpur

verilog vlsi verilog-hdl vlsi-design

Updated Mar 10, 2024
Verilog

himanshushah05 / VLSI_design_multipliers

Star

This repository holds some different architectures for multipliers which have been used alongwith verilog code and testbench as well.

verilog wallace-tree-multiplier multiplier vlsi-design dadda-tree-multiplier

Updated Jun 8, 2023
Verilog

Introducing an innovative H.264 decoder project with QCIF resolution, designed to enhance video playback performance. This open-source GitHub repository offers a robust solution for decoding H.264 video streams, enabling seamless playback on various platforms.

opensource vlsi-design uniccass

Updated Oct 27, 2023
Verilog

kputhanangadi / verilog_projects

Star

A compilation of various projects programmed fully in Verilog.

verilog vlsi-design

Updated Apr 20, 2023
Verilog

geitanksha / vlsi-design

Star

Created AMD-Am2901 chip clone (4-bit ALU) with Cadence Virtuoso from a transistor level, manually creating datapath and generating control via CAD. Skills employed: Cadence Virtuoso, Logic (VLSI) Design, Verilog

verilog cadence-virtuoso logic-design vlsi-design

Updated Jul 2, 2023
Verilog

SuhailAhamed2000 / full-adder

Star

A full adder circuit is central to most digital circuits that perform addition or subtraction. It is so called because it adds together two binary digits, plus a carry-in digit to produce a sum and carry-out digit.1 It therefore has three inputs and two outputs.

digital verilog vlsi vlsi-design

Updated Jul 25, 2021
Verilog

MSaaad / vlsi-lab-tasks

Star

Codes performed in labs using Xilinx ISE 14.7

verilog vlsi-design verilog-code

Updated Sep 15, 2020
Verilog

MuballighHossain / CMOS_3_To_8_Decoder_VLSI

Star

verilog vlsi cmos vlsi-design verilog-code cmos-circuits

Updated Aug 20, 2022
Verilog

MuballighHossain / Full_Adder_Priority_Encoder_VLSI

Star

encoder fulladder vlsi vlsi-circuits vlsi-design priority-encoder

Updated Aug 20, 2022
Verilog

Emmanuel-Innocent / Round_Robin_Arbiter

Star

This is the design of a work-conserving Round Robin Arbiter, with four (4) request queues. This was implemented on an FPGA(DE10-Lite).

fpga embedded-systems scheduling-algorithms vlsi-design

Updated Aug 11, 2022
Verilog

VardhanSuroshi / Vedic-Multiplier-From-RTL2GDS

Star

GitHub repository dedicated to VLSI ASIC Design using open-source tools! A simple Vedic Multiplier is Forged, through the entire RTL to GDS process that meets various PPA

vlsi physical-design vlsi-design rtl-gds

Updated Jan 23, 2024
Verilog

MuballighHossain / VLSI_FSM_Verilog_Simulation

Star

fsm verilog hdl vlsi verilog-hdl vlsi-circuits verilog-project vlsi-design

Updated Aug 20, 2022
Verilog

skynatepro / MIPS32

Star

Design of 32-bit MIPS Processor

verilog-project vlsi-design verilog-code

Updated Aug 10, 2022
Verilog

ammarmalik17 / Verilog_Adders

Star

This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.