Microshift Compression: An Efficient Image Compression Algorithm for Hardware
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Updated
Apr 21, 2021 - Verilog
Microshift Compression: An Efficient Image Compression Algorithm for Hardware
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
This repo contains golden vector and randomization testbenches for SRAM module.
UART - RTL Design and Verification
designed to control the doors, windows, fire alarm and the temperature. Each process being automated is associated with a sensor.
TicTacToe game using verilog hdl and implementation in spartan-3 FPGA board
The Repository contains the code of various Digital Circuits
VLSI Design - Spring 2022
Design of 32-bit MIPS Processor
Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator
Codes performed in labs using Xilinx ISE 14.7
Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode (either serial or parallel) by shifting it either towards right or towards left. In other words, a combined design of unidirectional (either right- or left-shift of data bits as in case of SISO, SIPO, PISO, PIPO) and bidirectional shift re…
A full adder circuit is central to most digital circuits that perform addition or subtraction. It is so called because it adds together two binary digits, plus a carry-in digit to produce a sum and carry-out digit.1 It therefore has three inputs and two outputs.
This repository contains code files for VLSI Laboratory - EC39004, conducted in Spring 2024 at IIT Kharagpur
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