A Dual Core MIPS CPU. Feature 11 32-bit instructions, 8-bit datapath, Arbiter, MMU, and ROM. Verified using RAM module which encoded a Fibonacci program and via Randomized test bench.
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Updated
Mar 6, 2023 - HTML
A Dual Core MIPS CPU. Feature 11 32-bit instructions, 8-bit datapath, Arbiter, MMU, and ROM. Verified using RAM module which encoded a Fibonacci program and via Randomized test bench.
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