Test checks for source-net-connected PCB vias

[seveibar]

Summary

• cover a PCB trace overlapping a via assigned directly through source_net_id
• verify same-net contact produces neither an overlap error nor a clearance error
• reproduce the live false-positive shape from the nRF52810 tracker
• add circuit-json-to-connectivity-map 0.0.27 as an explicit development dependency

Depends on merged tscircuit/circuit-json-to-connectivity-map#35.
Part of tscircuit/tscircuit#4205.

Validation

• focused overlap/clearance regression passes
• build passes
• format check passes with its existing large-fixture notices
• git diff --check

[tscircuitbot]

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PR Rating: ⭐⭐
Impact: Minor

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