Ready doesn't go high in tests (FIRRTL)

[immesys]

Forgive me, I'm new to Chisel, so this could be user error.

I am struggling to get testing to work. I get tons of warnings that look like this:

WARNING: external module "AsyncResetReg"(tl.commandFifo.sink.ridx_gray:AsyncResetReg)was not matched with an implementation

For this test, I have both enq_clock and deq_clock driven with the same clock (and both resets are the same reset). When I run tests, for some reason, io.enq.ready never goes high. I am using the default testing backend (not verilator).

Is there something I need to do to get this to work with PeekPokeTester ?

[immesys]

Also, I should mention that the verilog generates fine, and I can generate FPGA bitstreams, so I am pretty sure the blackbox is being found okay (at least for that workflow, apparently it isn't for testing).

[immesys]

Also, this seems to work when I do use verilator, so I guess I am specifically asking how to get it to work with firrtl.

[chick]

I don't think this is user error. Support for this is still in the works. The treadle backend has been updated with an example (and some fixes that example required) that shows how it should be implemented. The next step is to have the chisel-testers and/or chisel-testers2 update to provide the necessary options and implementation. You should be able to get it going if you take a look at how treadle did it in its tests and port it to your test harness. Let me know if you need more guidance there.

I would suggest moving this issue as an enhancement requests to the freechipsproject/ testers issues.

Background: verilator is able to run blackboxed verilog code, but the scala-based backend (treadle, firrtl-interpreter) can't run verilog, so they need to have a scala implementation that emulates the verilog. It is unlikely that the interpreter backend will be upgraded to support this, its clock propagation model and blackbox api make it rather difficult to do there. But treadle should work if passed in the right stuff.

[chick]

I should point out also that the scala based backends are not robust enough at the current time to run rocket-chip. Looking at this repo a little more I think it could have a better test/example provide in src/test. I'll put it on my list of things to look into.

[edwardcwang]

Yeah, the crux of the issue is that AsyncQueue uses asynchronous-reset registers which are not natively supported in FIRRTL.