CLB pin mismatch between .net and .route files #241
Description
Expected Behaviour
(1) What is the way to find out that a particular pin number in .net file is same as some other pin number in .route file. How can we dump that information by running the tool?
(2) My understanding is that place & route is changing the netlist of .net file. How can I dump this new netlist (new .net file) ?
Current Behaviour
I am running VTR tool for a very small design for fpga xml file "k6_N10_mem32K_40nm.xml". (This xml file is having "equivalent" set to "true" for input pins of clb.)
For a particular clb, input pin numbers are not matching between .net and .route files.
For example: In .net file net "top^c" is connected to 4th input pin of clb (if we starting pin numbering from 0 for clb input pins). In .route file same net (top^c) is connected to pin number 18 of the clb.
If I want to generate bitstream for this fpga, then there is confusion because input pin order of clb is different in .net and .route files.
Following are few lines from the generated .net and .route files.
(1)
.net file:
open open open open top^c open open open open open open open open open open open open open open open open open open open open open open open open open open open open open open open open top^a top^b open
(2)
.route file:
Net 0 (top^c)
Node: 61 SOURCE (1,0) Pad: 13
Node: 85 OPIN (1,0) Pad: 13
Node: 265 CHANX (1,0) Track: 19
Node: 117 IPIN (1,1) Pin: 18
Node: 96 SINK (1,1) Class: 0
Net 1 (top^a)
Node: 55 SOURCE (1,0) Pad: 7
Node: 79 OPIN (1,0) Pad: 7
Node: 257 CHANX (1,0) Track: 11
Node: 133 IPIN (1,1) Pin: 34
Node: 96 SINK (1,1) Class: 0
Net 2 (top^b)
Node: 202 SOURCE (2,1) Pad: 4
Node: 226 OPIN (2,1) Pad: 4
Node: 385 CHANY (1,1) Track: 19
Node: 124 IPIN (1,1) Pin: 25
Node: 96 SINK (1,1) Class: 0