Need better error checking for repeat pins

[kmurray]

Originally reported on Google Code with ID 39

What steps will reproduce the problem?
1. Compiled attached architecture file
2. VPR crashes
3. Fix line 1224 and 1228 alm[5:4] to alm[5:5], rerun and the architecture is fine

What is the expected output? What do you see instead?


Please use labels and text to provide additional information.

Reported by JasonKaiLuu on 2012-08-14 20:12:37

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- _Attachment: [stratixiv_arch.xml](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-39/comment-0/stratixiv_arch.xml)_

[kmurray]

Better error checks/reporting is a thankless, never ending task that produces no papers.
 I'll deal with this later when I can batch a bunch of these software engineering items
together thus allowing a burst of work on small, unrelated issues.

Reported by JasonKaiLuu on 2012-08-14 20:18:38

[github-actions]

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[github-actions]

This issue has been marked stale for 15 days and has been automatically closed.