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Carry-chain bug #41

@kmurray

Description

@kmurray

Originally reported on Google Code with ID 48

This circuit has a cout -> a[0] and the same cout -> cin.  Placement code thinks that
all 3 output adders belong to the same carry-chain when in fact the adder connected
at a[0] does not belong.  Results in the swap code messing up and swapping the adder
with a[0] being fed by a carry-out to bad locations.

Search for net "top^ADD~5542-1[0]" in blif

Reported by JasonKaiLuu on 2012-11-08 00:01:10


- _Attachment: [jedit.xml](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-48/comment-0/jedit.xml)_ - _Attachment: [mkDelayWorker32B.pre-vpr.blif](https://storage.googleapis.com/google-code-attachments/vtr-verilog-to-routing/issue-48/comment-0/mkDelayWorker32B.pre-vpr.blif)_

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StaleVPRVPR FPGA Placement & Routing ToolbugIncorrect behaviour

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