IKS16bit

HomGate 300 MHz FPGA Build

Successfully builds and runs at 300 MHz on Xilinx Alveo U280 with Vitis 2023.2.

Changelog (since switchtrans)

RTL Fixes

• Split IKS accumulator into 10 independent 512-bit sub-accumulators (was single 5120-bit), eliminating ~4000 unroutable nets from BRAM fanout congestion
• Pipeline IKS addr comparison in AXISIKS (addrPipe + wrapBubble) to break critical path through address decomposition output queue
• Increase AXI4 register slices from 6 to 8 stages for better SLR crossing timing

Parameter & Build Fixes

• Derive totaliksknumbus and iksknumsegments from qbit parameter instead of hardcoding, supporting both 16-bit and 32-bit LWE configurations
• Use Congestion_SpreadLogic_high Vivado implementation strategy for reliable routing
• Bump TFHEpp and fix RTL for uint16_t lvl0param::T

Test

• NAND gate test passes on real FPGA: ~1.3 ms per gate

Timing

• WNS: -0.037 ns (residual violation in Xilinx HBM platform IP, not user RTL)
• 0 unroutable nets

Artifact

• HomGate_hw.xclbin: Pre-built bitstream for Xilinx U280 (xilinx_u280_gen3x16_xdma_1_202211_1)