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Harden target configuration validation - #333

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LunaStev merged 1 commit into
wavefnd:masterfrom
LunaStev:patch/target-validation
Aug 9, 2026
Merged

Harden target configuration validation#333
LunaStev merged 1 commit into
wavefnd:masterfrom
LunaStev:patch/target-validation

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@LunaStev

@LunaStev LunaStev commented Aug 9, 2026

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Summary

  • centralize supported targets in a feature-gated TargetSpec registry with exact triple matching
  • reject unsupported triples, CPUs, features, duplicate or conflicting feature settings, and invalid ABI combinations before frontend or LLVM work
  • use the shared registry for CLI target reporting, target attributes, linker selection, and backend target dispatch
  • report hosted/freestanding and object-format metadata consistently
  • add object-codegen coverage for every advertised target, CPU, feature toggle, and RISC-V ABI

Why

Target knowledge was duplicated across the CLI, runner, linker, and LLVM backend. Several paths used substring matching, so malformed triples could be classified as supported and reach backend assertions. The advertised target option lists also contained values that LLVM 21 did not safely accept: RISC-V rocket selected an RV32 CPU and AArch64 fp was ignored as an unknown feature.

This change establishes one exact target contract and validates user-provided target settings at the CLI boundary. Invalid settings now fail as usage errors with exit code 2 instead of reaching LLVM, emitting warnings, or surfacing compiler-internal failures.

Notable behavior

  • build, check, object generation, and --dry-run validate the effective target first.
  • JSON usage errors remain on stderr and do not contaminate stdout.
  • RISC-V CPU overrides use generic, generic-rv64, rocket-rv64, or sifive-u74.
  • AArch64 exposes LLVM's actual fp-armv8 feature name.
  • LP64F and LP64D reject explicitly disabled required floating-point features.
  • Linux RV64 remains intentionally unsupported in this PR; it will be added with its effective CPU/ISA/ABI contract in the next change.

Validation

  • cargo fmt --all -- --check
  • cargo test --locked --all-targets — 17 passed
  • cargo clippy --locked --all-targets -- -D warnings
  • cargo build --locked --release
  • target option object matrix with default features
  • target option object matrix with each of llvm-target-x86, llvm-target-aarch64, and llvm-target-riscv enabled independently
  • python3 tools/run_tests.py — 96 passed, 0 failed
  • all 13 examples pass wavec check
  • all 79 standard-library Wave modules pass wavec check

Centralize Wave target support in a feature-gated TargetSpec registry with exact triple matching, architecture metadata, hosted and freestanding classification, object formats, CPUs, features, and ABI overrides.

Reject unsupported triples, target CPUs, unsigned or unknown features, duplicate and conflicting feature settings, and invalid RISC-V ABI combinations before check, build, object generation, or dry-run can reach LLVM. Keep usage failures machine-readable with exit code 2 and without leaking backend panics or internal compiler errors.

Replace target substring heuristics in the CLI, runner, linker selection, target attributes, and LLVM backend with the shared registry and CodegenTarget mappings. Align advertised options with LLVM 21 by using rocket-rv64, permitting the generic RV64 CPU, and exposing fp-armv8 for AArch64.

Add regression coverage for malformed targets, CPU and feature errors, LP64F and LP64D requirements, exact target lookup, JSON diagnostics, target metadata, every advertised target/CPU/feature combination, feature-specific LLVM builds, warning-free object generation, and ELF, Mach-O, and COFF object-format consistency.
@LunaStev
LunaStev marked this pull request as ready for review August 9, 2026 02:12
@LunaStev
LunaStev merged commit fc3f22e into wavefnd:master Aug 9, 2026
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