VHDL Projects

VHDL component implementation of logic untis

Lab 1:

Implemented ALU logic for Optimized division
Implemented DivRegister logic for Division
Implemented Control logic for Division
Implemented Division logic using ALU, DivRegister, and Control for Optimized Division

Implemented Instruction decoder for Mips Processor
Implemented ALU Control to communicate with Decoder
Implemented Test Module that connects Instruction decoder and ALU control to work sychronously

Implemented Register module for reading 8-byte instruction address
Implemented ROM module which performs read-only, short for read-only memory
Implemented RAM module which is short for Random Access Memory, updating RAM memory

Name		Name	Last commit message	Last commit date
Latest commit History 45 Commits
MIPS-Processor		MIPS-Processor
ADDER.vhd		ADDER.vhd
ALU.vhd		ALU.vhd
ALU8_test.vhd		ALU8_test.vhd
ALUDiv_test.vhd		ALUDiv_test.vhd
ALU_8bit.vhd		ALU_8bit.vhd
ALU_Div.vhd		ALU_Div.vhd
ALU_test.vhd		ALU_test.vhd
Control.vhd		Control.vhd
DivReg_test.vhd		DivReg_test.vhd
DivRegister.vhd		DivRegister.vhd
Division.vhd		Division.vhd
Division_test.vhd		Division_test.vhd
Multiplexer.vhd		Multiplexer.vhd
Multiplexer_Test.vhd		Multiplexer_Test.vhd
README.md		README.md
mux2_1.vhd		mux2_1.vhd