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FPGAThis issue is related to FPGAThis issue is related to FPGAFeature requestRequest to add or improve something in WiremodRequest to add or improve something in Wiremod
Description
Mainly targetting addition/multiplication gates such that they dont always have to have 8 inputs - whether we'd be overriding the wire gates or adding special new ones i am unsure.
My idea is that the gate will always have 1 more input than youre currently using, so an add gate starts out with 1 input, and then when you connect that it gets 2 etc.
If we do override gates, here is my attempt at listing the biggest culprits:
Angle - Addition
Arithmetic - Add, Average, Multiply
Logic - All except for Not (Invert), however these are already replicated as CPU gates
Selection - Maximum (Largest), Minimum (Smallest)
String - Concatenate
Vector - Addition, Multiplexer, Select
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FPGAThis issue is related to FPGAThis issue is related to FPGAFeature requestRequest to add or improve something in WiremodRequest to add or improve something in Wiremod