WireDAQ v0.3.0

Version numbers are bumped and reconciled across pyproject.toml, Cargo.toml, and
CMakeLists.txt; tag v0.3.0 to publish to PyPI.

Added

• Per-node clock reconstruction (ADR 0002). The ground station fits a per-node
  ClockModel (online least squares) against its reference clock, recovering each node's
  drift and mapping node timestamps onto one timeline. Recovered drift matches the injected
  drift_ppm within < 0.5 ppm; jitter widens the confidence interval without biasing it.
• wiredaq-clocksync CLI — demos drift recovery and cross-node timeline alignment.
• CsvLogger writes a reconstructed t_ref_us column so drifted nodes align in the export.
• Rust/Lua backend now runs a seeded link simulation — per-packet loss / duplication /
  jitter / reorder with a decode-side receiver, plus executed faults and assertions
  tables; unknown fault kinds are rejected. Its golden vectors are read from the shared
  vectors.json (decode + re-encode) and cargo test runs in CI.
• Hardware-in-the-loop seam. SerialPortTransport (a receive-side ByteStreamTransport
  backed by a real serial device) lets a real board drop in behind the same port the
  simulated serial link used; the existing StreamReceiver → Collector run unchanged.
  Verified without hardware by a loopback test; docs/bring-up-log-template.md captures the
  predicted-vs-observed comparison once a board is attached. pyserial is an optional
  hardware extra — the core stays standard-library-only.

Fixed

• RawFrameLogger and StreamReceiver handle HEARTBEAT frames correctly (were re-encoded
  as / rejected as data, causing byte-mismatched archives and phantom loss).
• Clock drift is no longer quantized to zero at the CLI-default ppm (float accumulation).
• C++ wrapper rejects sample counts that overflow the uint8 wire field instead of
  silently truncating.
• Impairment corruption is always classified as CRC, not framing.
• Decoders (Python / C / Rust) fail closed on control-plane shape: a HEARTBEAT with nonzero
  channel/sample counts is rejected.
• C++ encode() dispatches on msg_type, so encode(decode(heartbeat)) round-trips.
• Collector distinguishes a stale duplicate from a genuine reorder (bounded seen-set), so a
  late duplicate no longer decrements real loss; reorder is counted only on an actual overtake.

Docs

• Fixed stale test counts, softened overclaims ("avionics-grade", "HIL is a drop-in",
  "wired to the schema"), named ADR deciders, and repaired the two broken demo-site links.

WireDAQ v0.2.0

Second release. Adds a controllable clock, a real link-latency model, a cross-language HEARTBEAT control message with node liveness, and the project's first test/conformance CI.

Highlights

• Clock seam (wiredaq.daq_sim.core.clock): SimClock (virtual, deterministic) + WallClock (live), so timing is reproducible in tests.
• Link latency + jitter in ImpairmentTransport (delay_us / jitter_us), delivered via a clock-keyed release buffer. Jitter produces emergent reordering. New CLI flags --delay-us / --jitter-us.
• HEARTBEAT control-plane message across all three codecs (Python, C firmware, C++): a node liveness / clock beacon, held to the same golden vectors as SAMPLE_BLOCK. Collector.stale_nodes() flags silent nodes. New CLI flags --heartbeat-every / --stale-after-us.
• CI (.github/workflows/tests.yml): pytest on Python 3.10–3.12, package build + twine check, and a cross-language conformance job for the C and C++ codecs.
• Independent-oracle codec test (table-driven CRC + hand byte-layout) so codec bugs can't hide behind a shared implementation.

The 4 original SAMPLE_BLOCK golden vectors are byte-identical to 0.1.0 — no wire-format drift.

Full changelog: v0.1.0...v0.2.0

WireDAQ v0.1.0

First tagged release of WireDAQ — a wire-ready data-acquisition (DAQ) architecture simulator. MIT licensed.

Highlights

• Python package wiredaq (src layout, zero runtime deps) with console scripts wiredaq-slice / wiredaq-serial.
• One enforced wire contract: packet_schema.yaml + golden vectors, reproduced byte-for-byte by three codecs — Python, C firmware (firmware/), and a find_package-able C++ library (wiredaq::codec).
• Runtime: four ports + adapters — in-process / impairment / real-UDP / serial transports, synthetic + replay nodes, datagram + stream receivers, collector with per-node loss/reorder/duplicate detection, CSV / metrics / raw-log / live-dashboard sinks.
• Record & replay for bit-exact session reproduction.
• Decisions: ADR 0001 accepted; ADR 0002 (clock domain) & 0003 (wire-format specifics) proposed.
• Tests: 18 Python checks + 4 firmware golden vectors + a C++ conformance test.
• Interactive demo: https://wuisabel-gif.github.io/WireDAQ/

Install

Once the PyPI Trusted Publisher is configured: pip install wiredaq. Until then, install the attached wheel, or pip install -e . from a checkout.