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WireDAQ v0.2.0

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@wuisabel-gif wuisabel-gif released this 22 Jun 08:03
v0.2.0
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Learn about vigilant mode.

Second release. Adds a controllable clock, a real link-latency model, a cross-language HEARTBEAT control message with node liveness, and the project's first test/conformance CI.

Highlights

  • Clock seam (wiredaq.daq_sim.core.clock): SimClock (virtual, deterministic) + WallClock (live), so timing is reproducible in tests.
  • Link latency + jitter in ImpairmentTransport (delay_us / jitter_us), delivered via a clock-keyed release buffer. Jitter produces emergent reordering. New CLI flags --delay-us / --jitter-us.
  • HEARTBEAT control-plane message across all three codecs (Python, C firmware, C++): a node liveness / clock beacon, held to the same golden vectors as SAMPLE_BLOCK. Collector.stale_nodes() flags silent nodes. New CLI flags --heartbeat-every / --stale-after-us.
  • CI (.github/workflows/tests.yml): pytest on Python 3.10–3.12, package build + twine check, and a cross-language conformance job for the C and C++ codecs.
  • Independent-oracle codec test (table-driven CRC + hand byte-layout) so codec bugs can't hide behind a shared implementation.

The 4 original SAMPLE_BLOCK golden vectors are byte-identical to 0.1.0 — no wire-format drift.

Full changelog: v0.1.0...v0.2.0

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