A safety-verifying software-to-hardware compiler that bridges high-level continuous-variable (CV) logic with silicon-photonic programmable processors (originally framed as 1-bit Photonic Arithmetic Logic Units, PALUs). The framework parses Blackbird CV code, solves continuous voltage trajectories on the geometric phase space, formally verifies them against hardware safety constraints, and streams the resulting waveforms to the DACs driving the photonic chip. It is a verifying compiler (it proves properties of the waveforms it emits), not a verified compiler (a proof of the compiler itself).
All project documentation lives in one place: docs/report/, the technology report (introduction, design evolution, technical description, testing, plus appendices for the mathematics, the build plan, and the original master specification).
syntra_pulse/ Python compiler — frontend, solver, verifier, HAL (AGPLv3)
tests/ Test suite (AGPLv3)
specs/ TLA+ models, C4 architecture, JSON schemas (CC-BY-4.0)
docs/report/ Technology report — all project documentation (CC-BY-4.0)
This project is dual-licensed by artifact type:
- Source code (
syntra_pulse/,tests/, build scripts, configuration code) is licensed under the GNU Affero General Public License v3.0 — seeLICENSE. - Documentation, specifications, and design artifacts (
docs/,specs/,*.mdfiles, diagrams, TLA+ models, JSON schemas) are licensed under the Creative Commons Attribution 4.0 International License — seeLICENSE-DOCS.
The AGPLv3 requires that derivative works and network-deployed services based on this code also be released under AGPLv3. Organizations wishing to integrate Syntra Pulse into proprietary, closed-source hardware stacks or commercial products without AGPL obligations can obtain a commercial license. Contact the maintainers to inquire.
See CONTRIBUTING.md. Contributions to the source tree require sign-off so the project can continue to be offered under both AGPL and commercial terms.