An open, executable baseline for testing a differential charge-domain matrix engine without pretending that simulated behavior is silicon.
Maturity: Behavioral-model released — stage 1 in a six-stage ledger numbered 0 through 5. There is no verified transistor-level design, no PDK layout, no fabricated device, and no measured silicon result.
The repository connects four things that are often discussed separately:
- a deterministic 8 x 8 signed fixed-point behavioral model;
- explicit quantization, mismatch, offset, noise, drift, clipping, ADC, and calibration effects;
- a host runtime and future memory-mapped driver contract; and
- reproducible receipts plus a whole-system measurement boundary for later SPICE, layout, and silicon evidence.
Every numeric result must carry its configuration, device seed, operation seed, inputs, weights, reference output, observed output, error metrics, and receipt hash. The nominal six-bit magnitude plus sign is an unverified design target, not a measured precision result.
The model has no third-party runtime dependency and requires Python 3.11 or newer.
python -m venv .venv
# POSIX: . .venv/bin/activate
# Windows PowerShell: .venv\Scripts\Activate.ps1
python -m pip install -e .
python -m analog_matmul_lab baselineRun the activation command for your platform before the install command.
Run the verification suite:
python -m unittest discover -s tests -v
python -m compileall -q src tests
python scripts/check_spdx.py
python scripts/check_register_contract.pyMinimal API example:
from analog_matmul_lab import ModelConfig, SimulatorDevice
config = ModelConfig(device_seed=7, noise_sigma=0.002)
device = SimulatorDevice(config)
device.load_weights([[8 if row == column else 0 for column in range(8)] for row in range(8)])
report = device.matvec([32, 16, 8, 4, -4, -8, -16, -32], operation_seed=11)
print(report.output)
print(report.receipt["receipt_sha256"])The checked-in baseline command uses deterministic synthetic data and emits a canonical JSON receipt. It does not benchmark physical performance.
The planned analog concept is a differential, charge-domain, switched-capacitor matrix engine in ordinary CMOS. Signed weight codes select positive or negative segmented capacitor branches; row DAC voltages are sampled, charge is redistributed onto paired column accumulators, and a time-multiplexed differential readout digitizes each dot product. Known-code sweeps provide per-column affine calibration, with richer correction permitted only when data justifies it.
That circuit topology is an unverified concept, not a schematic or validated
design. docs/ARCHITECTURE.md makes the signaling, accumulation, readout,
calibration, and digital-boundary assumptions explicit. The future 4 x 4
characterization macro is intentionally smaller than the 8 x 8 research target
but activates sixteen elements, matching the first precision gate.
The stack models forward matrix-vector products (W·x), transpose matrix-vector
products (Wᵀ·g), and host-computed outer-product weight updates applied by
digital weight reprogramming. This supports inference and hybrid hardware-aware
or hardware-in-the-loop training research in simulation.
It does not claim or implement on-chip analog weight updates, analog gradient computation, in-memory training on non-volatile devices, a complete training accelerator, or any measured speed, accuracy, energy, area, or yield result. All numeric parameters—including nominal six-bit magnitude plus sign—are unverified design targets or declared simulation settings.
This project does not claim to be the first analog-AI simulator. IBM's AIHWKit provides mature analog-aware training and inference simulation, and Sandia's CrossSim models analog in-memory computing accuracy. Those projects should be considered before using this one.
This stack explores a narrower research contract:
- include conversion, memory movement, control, calibration, and repeated work in any future energy claim;
- make every example emit a seeded, machine-verifiable receipt;
- keep the software API, register map, C header, and digital shell aligned; and
- advance claims only through a public six-stage maturity ledger.
See docs/PRIOR_ART.md for positioning and citations. These differentiators are
project objectives, not patentability or novelty conclusions.
src/analog_matmul_lab/ Deterministic model, calibration, runtime, receipts
hardware/include/ Apache-licensed portable C interface
hardware/spec/ Register and data-format contract
hardware/rtl/ CERN-OHL-P digital shell and analog black-box boundary
hardware/spice/ Optional technology-independent examples
docs/ Architecture, maturity, measurement, tapeout, grants
examples/ Synthetic configurations and receipts
tests/ Model, runtime, receipt, and contract verification
scripts/ Reproducible local checks
The stages are:
- Concept
- Behavioral-model released (current)
- SPICE-verified
- Layout-verified
- Fabricated
- Silicon-measured
Stage criteria are in docs/MATURITY.md. A future accelerator claim remains
behind both of these go/no-go targets:
- at least six effective bits with at least sixteen active elements under a declared workload; and
- at least a 3x whole-system useful-MAC energy advantage over a named digital baseline, including conversion, memory, control, calibration, and repeats.
These are targets, not present results.
The leading research path is a 4 x 4 characterization macro in an open 130 nm
flow, with IHP SG13G2 and Tiny Tapeout's analog interface under evaluation.
Eligibility, schedule, pin fit, cost, and fabrication are all unverified and no
tapeout is authorized. See docs/TAPEOUT.md.
Read CONTRIBUTING.md before submitting changes. Contributions use Developer
Certificate of Origin sign-off, per-file SPDX identifiers, and the existing
hardware/software license boundary. Never submit confidential PDK data,
customer material, or source copied from another implementation.
This is research software and unverified hardware material. It is not a
production, safety-qualified, or security-hardened component. See SECURITY.md.
Hardware design material is under CERN-OHL-P-2.0. Software, tests, portable C
headers, data formats, and general documentation are under Apache-2.0. The
controlling license is the SPDX identifier in each file; complete texts are in
LICENSES/. Human/AI contribution boundaries are recorded in PROVENANCE.md.
This repository is published as an intentional public disclosure. Versioned, tagged releases are intended to document these concepts as published prior art as of their release dates. No representation or warranty is made about the legal effect of this disclosure in any jurisdiction, and this disclosure is not a substitute for legal advice.
This project is maintained as part of YY's open research program. For bounded, source-preserving forensic data and document work, see YY's paid services.