This project showcases the entire design process from an RTL description of an 8-bit Synchronous SRAM Module to GDSII. Though the Schematic designs are not shown, those were also done in Cadence Virtuoso.
- Standard cells shown in Project 4 and Project 5 are not entirely accurate. Pin pitch, and subsequently cell width, was signifcantly shrunken down for Project 6.
- Standard cells are too tall. The D Flip-Flop will end up being the tallest cell in the library, and it could be shrunken down by at least 2 pin pitches, if not at least 4.
- In terms of physical design, this ends up being much closer to a register file than an SRAM cell, as the design uses DFFs instead of the standard 6T SRAM cell.
- Subsequently, the total design area could also be significantly shrunk down.