Support imx93 video pll driver

boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_ddr.dts

@@ -1,12 +1,13 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 /dts-v1/;
 
 #include "imx93_evk_mimx9352_m33.dts"
+#include <dt-bindings/mipi_dsi/mipi_dsi.h>
 
 / {
 	model = "NXP i.MX93 EVK board DDR variant";
@@ -18,6 +19,18 @@
 
 	ddr: memory@84000000 {
 		device_type = "memory";
-		reg = <0x84000000 DT_SIZE_M(4)>;
+		reg = <0x84000000 DT_SIZE_M(32)>;
 	};
 };
+
+&lpi2c2 {
+	pinctrl-0 = <&i2c2_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+zephyr_lcdif: &lcdif {};
+
+display_i2c: &lpi2c2 {};
+
+zephyr_mipi_dsi: &mipi_dsi {};

boards/shields/nxp_mx8_dsi_oled1a/Kconfig.defconfig

@@ -0,0 +1,39 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SHIELD_NXP_MX8_DSI_OLED1A
+
+config GPIO
+	default y
+
+config GPIO_ADP5585
+	default y
+
+if DISPLAY
+
+if LVGL
+
+config LV_Z_VDB_SIZE
+	default 100
+
+config LV_Z_DOUBLE_VDB
+	default y
+
+config LV_Z_BITS_PER_PIXEL
+	default 32
+
+config LV_Z_FULL_REFRESH
+	default y
+
+choice LV_COLOR_DEPTH
+	default LV_COLOR_DEPTH_32
+endchoice
+
+endif # LVGL
+
+endif # DISPLAY
+
+endif # SHIELD_NXP_MX8_DSI_OLED1A

boards/shields/nxp_mx8_dsi_oled1a/Kconfig.shield

@@ -0,0 +1,8 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SHIELD_NXP_MX8_DSI_OLED1A
+	def_bool $(shields_list_contains,nxp_mx8_dsi_oled1a)

boards/shields/nxp_mx8_dsi_oled1a/doc/index.rst

@@ -0,0 +1,49 @@
+.. _nxp_mx8_dsi_oled1a:
+
+NXP MX8 DSI OLED1A Panel
+#########################
+
+Overview
+********
+
+The NXP MX8 DSI OLED1A shield is a high-resolution OLED display panel
+designed for use with NXP i.MX8 series processors. This panel provides
+excellent color reproduction and contrast ratio through OLED technology.
+The display shield connects via MIPI DSI interface and offers superior visual
+performance for embedded applications.
+
+More information about the panel can be found
+at the `NXP MX8 DSI OLED1A Shield website`_.
+
+Current supported displays
+==========================
+
++--------------+------------------------------+
+| Display      | Shield Designation           |
+|              |                              |
++==============+==============================+
+| MX8 DSI      | nxp_mx8_dsi_oled1a           |
+| OLED1A       |                              |
++--------------+------------------------------+
+
+Programming
+***********
+
+Correct shield designation (see the table above) for your display must
+be entered when you invoke ``west build``.
+
+For example:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/subsys/display/lvgl
+   :board: imx93_evk/mimx9352/m33/ddr
+   :shield: nxp_mx8_dsi_oled1a
+   :goals: build
+
+References
+**********
+
+.. target-notes::
+
+.. _NXP MX8 DSI OLED1A Shield website:
+   https://www.nxp.com/part/MX8-DSI-OLED1A

boards/shields/nxp_mx8_dsi_oled1a/nxp_mx8_dsi_oled1a.overlay

@@ -0,0 +1,90 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/display/panel.h>
+
+/ {
+	chosen {
+		zephyr,display = &lcdif;
+	};
+};
+
+&media_blk_ctrl {
+	status = "okay";
+};
+
+&video_pll {
+	compatible = "nxp,imx93-video-pll";
+	rdiv = <1>;
+	mfi = <121>;
+	mfn = <0>;
+	mfd = <1>;
+	odiv = <6>;
+	pll-frequency = <484000000>;
+	status = "okay";
+};
+
+&zephyr_lcdif {
+	width = <1080>;
+	height = <1920>;
+	pixel-format = "argb-8888";
+	media-axi-clk-rate = <400000000>;
+	media-apb-clk-rate = <133333334>;
+	status = "okay";
+
+	display-timings {
+		compatible = "zephyr,panel-timing";
+		hsync-len = <2>;
+		hfront-porch = <20>;
+		hback-porch = <34>;
+		vsync-len = <2>;
+		vfront-porch = <10>;
+		vback-porch = <4>;
+		de-active = <0>;
+		pixelclk-active = <0>;
+		hsync-active = <1>;
+		vsync-active = <1>;
+		clock-frequency = <121000000>;
+	};
+};
+
+&zephyr_mipi_dsi {
+	nxp,dc = <&lcdif>;
+	dpi-color-coding = "24-bit";
+	dpi-video-mode = "non-burst-sync-pulse";
+	dphy-ref-frequency = <24000000>;
+	data-rate-clock = <726000000>;
+	status = "okay";
+
+	rm67199_panel@0 {
+		compatible = "raydium,rm67199";
+		reg = <0>;
+		bl-gpios = <&gpio_exp0 10 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio_exp0 9 GPIO_ACTIVE_HIGH>;
+		data-lanes = <4>;
+		pixel-format = <MIPI_DSI_PIXFMT_RGB888>;
+		status = "okay";
+	};
+};
+
+&display_i2c {
+	status = "okay";
+
+	mfd0: adp5585@34 {
+		compatible = "adi,adp5585";
+		reg = <0x34>;
+		status = "okay";
+
+		gpio_exp0: adp5585_gpio {
+			compatible = "adi,adp5585-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <13>;
+			gpio-reserved-ranges = <5 3>;
+			status = "okay";
+		};
+	};
+};

boards/shields/nxp_mx8_dsi_oled1a/shield.yml

@@ -0,0 +1,6 @@
+shield:
+  name: nxp_mx8_dsi_oled1a
+  full_name: NXP MX8-DSI-OLED1A
+  vendor: nxp
+  supported_features:
+    - display

boards/shields/waveshare_dsi_lcd/boards/frdm_imx93_mimx9352_a55.overlay

@@ -59,3 +59,14 @@
 &dsi_panel {
 	mipi-dsi = <&mipi_dsi>;
 };
+
+&video_pll {
+	compatible = "nxp,imx93-video-pll";
+	rdiv = <1>;
+	mfi = <200>;
+	mfn = <0>;
+	mfd = <1>;
+	odiv = <12>;
+	pll-frequency = <400000000>;
+	status = "okay";
+};

drivers/display/CMakeLists.txt

@@ -37,6 +37,7 @@ zephyr_library_sources_ifdef(CONFIG_NT35510 display_nt35510.c)
 zephyr_library_sources_ifdef(CONFIG_OTM8009A display_otm8009a.c)
 zephyr_library_sources_ifdef(CONFIG_RENESAS_RA_GLCDC display_renesas_ra.c)
 zephyr_library_sources_ifdef(CONFIG_RM67162 display_rm67162.c)
+zephyr_library_sources_ifdef(CONFIG_RM67199 display_rm67199.c)
 zephyr_library_sources_ifdef(CONFIG_RM68200 display_rm68200.c)
 zephyr_library_sources_ifdef(CONFIG_SH1122 display_sh1122.c)
 zephyr_library_sources_ifdef(CONFIG_SSD1306 ssd1306.c)

drivers/display/Kconfig

@@ -45,6 +45,7 @@ source "drivers/display/Kconfig.otm8009a"
 source "drivers/display/Kconfig.renesas_lcdc"
 source "drivers/display/Kconfig.renesas_ra"
 source "drivers/display/Kconfig.rm67162"
+source "drivers/display/Kconfig.rm67199"
 source "drivers/display/Kconfig.rm68200"
 source "drivers/display/Kconfig.sdl"
 source "drivers/display/Kconfig.sh1122"

drivers/display/Kconfig.mcux_lcdifv3

@@ -7,7 +7,6 @@ menuconfig DISPLAY_MCUX_LCDIFV3
 	default y
 	depends on DT_HAS_NXP_IMX_LCDIFV3_ENABLED
 	depends on CLOCK_CONTROL
-	select INIT_VIDEO_PLL
 	help
 	  Enable support for mcux LCDIFV3 driver.
 

drivers/display/Kconfig.rm67199

@@ -0,0 +1,10 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config RM67199
+	bool "RM67199 display controller driver"
+	default y
+	select MIPI_DSI
+	depends on DT_HAS_RAYDIUM_RM67199_ENABLED
+	help
+	  Enable driver for RM67199 display controller.

drivers/display/display_mcux_lcdifv3.c

@@ -270,7 +270,7 @@ static int mcux_lcdifv3_init(const struct device *dev)
 	LCDIFV3_SetLayerSize(base, 0, display_config.panelWidth, display_config.panelHeight);
 	LCDIFV3_EnableLayer(base, 0, true);
 	LCDIFV3_EnablePlanePanic(base);
-	LCDIFV3_SetLayerBufferAddr(base, 0, (uint64_t)data->fb[0]);
+	LCDIFV3_SetLayerBufferAddr(base, 0, (uint32_t)(uintptr_t)data->fb[0]);
 	LCDIFV3_TriggerLayerShadowLoad(base, 0);
 	LCDIFV3_EnableInterrupts(base, kLCDIFV3_VerticalBlankingInterrupt);