BitRoute — VHDL Memory Router

A synchronous VHDL module that decodes a serial bitstream into a memory address and routes the memory's output to one of four channels.

🌟 Highlights

• Decodes a serial input stream into a 2-bit channel selector and a memory address using a single finite-state machine.
• Routes an 8-bit memory value to one of four independent output channels (o_z0–o_z3) based on the decoded selector.
• Fully synchronous design with a clean, single-cycle reset and a one-cycle o_done completion pulse.
• Compact, single-entity implementation written in standard VHDL with no third-party dependencies.
• Includes a written project report describing the design and verification approach.

ℹ️ Overview

BitRoute is a small synchronous hardware module that reads a serial sequence of bits, uses the first two bits to pick one of four output channels, and uses the remaining bits (up to 16) to address an external memory. Once the input sequence ends, the module reads the addressed memory location and drives the resulting 8-bit value onto the selected channel.

The module is built around a finite-state machine (FSM) that shifts in bits on every clock cycle while i_start is asserted, then performs the memory read and output steps automatically. It is aimed at students and hobbyists studying digital logic design and finite-state machines, and can be dropped into a VHDL simulation or synthesis project as a self-contained component.

This module was developed as coursework for the Reti Logiche (Logic Networks) course at Politecnico di Milano, academic year 2022–2023.

🧩 How It Works

1. The module waits for i_start to go high, then starts sampling i_w on every rising edge of i_clk.
2. The first serial bit is stored as the high bit of the 2-bit channel selector.
3. The second serial bit completes the selector (00–11), choosing between o_z0, o_z1, o_z2 and o_z3.
4. While i_start stays high, up to 16 further bits are shifted in to build the memory address.
5. When i_start goes low, the module drives the address on o_mem_addr and asserts o_mem_en to trigger a read.
6. After one clock cycle, the returned i_mem_data value is latched into the register of the selected channel.
7. The latched value is presented on the selected output channel and o_done is asserted for one clock cycle.
8. The FSM returns to its initial state, ready to decode a new serial sequence.

🚀 Usage

Instantiate the project_reti_logiche entity in your own testbench or design, then drive i_start/i_w to send a channel selector followed by an address:

router_inst : entity work.project_reti_logiche
    port map (
        i_clk       => clk,
        i_rst       => rst,
        i_start     => start,
        i_w         => w,
        o_z0        => z0,
        o_z1        => z1,
        o_z2        => z2,
        o_z3        => z3,
        o_done      => done,
        o_mem_addr  => mem_addr,
        i_mem_data  => mem_data,
        o_mem_we    => mem_we,
        o_mem_en    => mem_en
    );

Example sequence: with i_start = '1', feed the bits 1, 0 (selects o_z2) followed by the desired address bits, then deassert i_start. One clock cycle later, o_done pulses high and the memory value at that address appears on o_z2.

This repository does not include a simulation testbench; write your own to drive i_clk/i_w/i_start and observe the outputs.

⬇️ Installation

Requirements

• A VHDL-93 or VHDL-2008 compatible simulator or synthesis tool (e.g. GHDL, ModelSim, Vivado, Quartus).
• Git.

Setup

git clone https://github.com/AlessandroAssini/bitroute-vhdl.git
cd bitroute-vhdl

Add src/project_reti_logiche.vhd to your simulation or synthesis project. No further configuration is required.

📁 Project Structure

bitroute-vhdl-main/
├── src/
│   └── project_reti_logiche.vhd  # Entity and architecture (FSM-based router)
├── docs/
│   └── Report.pdf                # Project report (Italian)
├── Project-code.vhd               # Original VHDL source from the remote repository
├── Report.pdf                     # Original report from the remote repository
└── README.md

🛠️ Technologies

• Language: VHDL (IEEE STD_LOGIC_1164)
• Design style: Synchronous, Moore-style finite-state machine

📄 License

This project is licensed under the MIT License.

🤝 Contributing

Contributions are welcome. If you find a bug, have a suggestion, or want to propose a change:

• open an issue describing the problem or idea;
• submit a pull request with your proposed change.

✍️ Authors

• Alessandro Assini
• Riccardo Antonelli

Developed as coursework for the Reti Logiche course at Politecnico di Milano (academic year 2022–2023).

📚 Documentation

• Project report (Italian)