2: Tools Requirements

This project has been tested intensively using Altera's Design Suite version 14.0 Specifically:

1. Quartus II version 14.0 has been used to synthesize the Verilog implementation
2. ModelSim Altera Edition version 10.0d (modelsim_ase) has been used to simulate the Verilog implementation.

Furthermore, the run-in-batch synthesis and simulation flow managers have been implemented using C-Shell, hence a /bin/csh should be available in the machine