3: Directory Structure

• README : Read this first!
• LICENSE : BSD 3-Clause ("BSD New" or "BSD Simplified") license
• fpga14-paper.pdf : ACM/SIGDA Intl Symp. on Field-Programmable. Gate Arrays (FPGA'14) paper
• fpga14-slides.pdf: ACM/SIGDA Intl Symp. on Field-Programmable. Gate Arrays (FPGA'14) slides
• sim : A C-shell script: A run-in-batch simulation flow manager
• syn : A C-shell script: A run-in-batch synthesis flow manager
• config.vh : Verilog: Generated by syn script, contains design parameters
• utils.vh : Verilog: Design pre-compile utilities
• mrram.v : Verilog: Multiread-RAM using bank replication; based on generic dual-ported RAM; optional 1 or 2-stage bypass
• dpram.v : Verilog: Generic dual-ported RAM/ optional 1 or 2-stage bypass
• mpram_gen.v : Verilog: Generic multiported-RAM; Old data will be read in case of RAW
• mpram_reg.v : Verilog: generic register-based multiported-RAM
• mpram_xor.v : Verilog: Multiported-RAM based on XOR implementation
• lvt_reg.v : Verilog: Register-based binary-coded LVT (Live-Value-Table)
• lvt_bin.v : Verilog: Binary-coded LVT (Live-Value-Table)
• lvt_1ht.v : Verilog: Onehot-coded LVT (Live-Value-Table)
• mpram_lvt_reg.v : Verilog: Multiported-RAM based on register-based LVT
• mpram_lvt_bin.v : Verilog: Multiported-RAM based on binary-coded LVT
• mpram_lvt_1ht.v : Verilog: Multiported-RAM based on onehot-coded LVT
• mpram.v : Verilog: Multiported-RAM: top hierarchy
• mpram_tb.v : Verilog: Multiported-RAM testbench
• mpram_wrp.v : Verilog: Multiported-RAM synthesis wrapper
• mpram.qpf : Quartus II Project File
• mpram.qsf : Quartus II Settings File
• syn.res : A list of synthesis results, each run in a separate line, including: frequency, resources usage, and runtime
• syn.res.example : Example results for 628 different designs
• sim.res : A list of simulation results, each run in a separate line, including all design styles
• log/ : Altera's logs and reports