Desktop Linux Falcon 26.1

The Arrow AXE5-Falcon is an Agilex 5 SoC development kit with a dual ARM Cortex-A55 HPS cluster and FPGA fabric. The Agilex 5 has no integrated GPU or display controller, so HDMI output requires FPGA assistance. The Altera VVP Video Frame Reader (VFR) IP core fills this role — it reads a Linux framebuffer from HPS DDR via AXI DMA and drives a 1920×1080p60 HDMI output through a chain of VVP video components in the FPGA fabric. With this driver in place the AXE5-Falcon boots directly to a Linux console on a standard HDMI monitor.

A DRM/KMS platform driver was developed to expose the VFR to Linux as a standard display device. DRM/KMS is the modern Linux display framework supporting Wayland, X11, and the kernel framebuffer console. It provides atomic modesetting, GEM buffer management, and fbdev emulation — allowing the Linux boot console to appear on the HDMI display without a user-space display manager. The framebuffer is allocated from the CMA pool as an 8 MB physically contiguous region, required because the VFR DMA master reads sequentially from a single base address and cannot follow a scatter-gather list. It is marked non-cacheable via dma-noncoherent in the device tree so CPU writes go directly to DDR, avoiding cache thrashing since the framebuffer is four times the size of the L3 cache.

The driver targets kernel 6.12 and above and has been ported through to 6.18, tracking API changes including the CMA-to-DMA helper rename, removal of the .date field from drm_driver, the addition of fbdev_probe as a required driver callback, and migration of fbdev client setup to drm_client_setup_with_fourcc().

Theory of Operation

At probe time the driver maps the VFR and CVO MMIO register blocks and verifies the VFR VID_PID. Both components operate in Lite mode, meaning the AXI4-S stream carries no embedded metadata — the CVO must be told the frame dimensions explicitly via its IMG_INFO registers before the VFR is started. The driver then registers the DRM KMS objects and triggers an initial atomic commit which programs the VFR buffer set descriptor with the CMA framebuffer physical address and starts the VFR in FREE_RUNNING mode.

The framebuffer format is XRGB8888 (4 bytes per pixel), chosen because 4-byte pixels divide evenly into any power-of-2 AXI bus width. The VFR uses Pixel Packing with 4 colour planes, reading 32 bits per pixel from DDR and outputting a 32-bit tdata AXI4-S stream to the CVO. The X padding byte passes through the pipeline and is discarded at the TFP410 which only uses the lower 24 data pins. Page flips update only the base address register, allowing the VFR to latch the new buffer without stopping.

The driver uses a no-vblank design since the VFR in Lite mode exposes no hardware interrupt. Flip events are delivered immediately in software via atomic_flush. The VFR and CVO data path run at 200 MHz (vid_clock) while the CVO timing generator and downstream display pipeline run at 148.5 MHz (fr_clock), with the CVO internal CDC FIFO bridging the two domains.

A block diagram of the hardware pipeline is shown below and is integrated into the GHRD as the Video Subsystem.

Golden Hardware Reference Design (GHRD)

The Golden Hardware Reference Design is an important part of a bootable Linux system and consists of the following components:

Hard Processor System (HPS)
- Dual core Arm Cortex-A55 processor
- HPS Peripherals:
  - SDMMC
  - EMAC
  - USB UART
  - I2C
  - USB 2.0
Multi-Ported FrontEnd(MPFE) for HPS External Memory Interface (EMIF)
FPGA Peripherals connected to Lightweight HPS-to-FPGA (LWS2F) AXI Bridge and JTAG to Avalon Master Bridge
- Four user push-button inputs
- Six user DIP switch inputs
- Four user I/O for RGB LED outputs
- JTAG UART
- System ID

The GHRD is constructed with a hierarchy. There is a top level that instantiates multiple subsystems. These include the following subsystems:

Board
Clock
HPS
EMIF
Peripheral
Video

The MIPI subsystem can be included to support dual camera inputs.

Configure the Board for the Demo

The following components are required for the demo:

AXE5-Falcon (TEI0183) development board,
USB C to C Cable (for the USB Blaster III, HPS UART, and power)
USB 2.0 Keyboard and mouse
HDMI Cable
1080p60 capable monitor
Ethernet Cable (not necessary, but useful)
USB Hard Drive (not necessary, but useful)
64GB SD card

Assemble the Hardware

Insert the SD card into the SD card cage on the underside of the board.
Attach the USB-C cable to the USB (J25) connector
Insert the HDMI cable. Connect it to a 1080p60-compatible monitor.
Connect a separate USB Keyboard and Mouse. Alternatively, a wireless mouse/keyboard dongle can be connected.
Optionally, connect an Ethernet cable and a USB hard drive.

Flash the FPGA configuration file

Download the FPGA jic image axe5_falcon_top.hps.jic

The FPGA JTAG chain will expose 1 or 2 devices when auto-detected from the programmer. Follow the appropriate instructions to program the Agilex 5 FPGA for either scenario.

Open a shell (Nios V Command Shell for Windows)

Determine the number of JTAG devices

    $ jtagconfig

One JTAG device
1) Arrow-USB-Blaster [ARA31601-TEI0004]
  0364F0DD   A5E(C065BB32AR0|D065BB32AR0)

Two JTAG devices
1) Arrow-USB-Blaster [ARA31601-TEI0004]
  4BA06477   ARM_CORESIGHT_SOC_600
  0364F0DD   A5E(C065BB32AR0|D065BB32AR0)

Option 1: One Device

    $ quartus_pgm -c 1 -m jtag -o "pvi;axe5_falcon_top.hps.jic@1"

Option 2: Two Devices

    $ quartus_pgm -c 1 -m jtag -o "pvi;axe5_falcon_top.hps.jic@2"

Program the device

This will take a few minutes to complete.

Connect to the target terminal

The AXE5-Falcon exposes two COM ports. One is driven from the FPGA and the other from the HPS. Select the higher COM port number that is exposed (HPS).

Launch a terminal program (like Tera Term VT or Putty) and connect using serial port
Select 115200 baud
Select the appropriate target COM port

Run the demo

Press the 'CONF' button to boot the demo. This will initiate the following boot process.

The Secure Device Manager (SDM) will read the jic file. This contains a partial FPGA image and the U-boot First Stage Boot Loader (FSBL). The partial image provides the HPS access to DDR and HPS I/O pins.
The SDM releases the Arm processor cluster in the Hard Processing System (HPS) from reset.
The Arm processor cluster then boots U-boot which completes the FPGA configuration. It then proceeds to boot Linux from the SD card
Rapsberry Pi Bookworm will take about two minutes to boot.
The terminal login credentials are username=arrow, password=falcon.

The image below shows the default splash screen. The Python interpreter has been opened and is running the RGB LED lightshow.

Build Instructions

Release Contents
Prerequisites
Set up the Environment
Build the Golden Hardware Reference Design
Build Arm Trusted Firmware
Build u-boot
Build the Linux kernel
Create an Integrated SOF file
Create an Integrated JIC file
Downloading via JTAG
Customize the Raspberry Pi Bookworm Distribution
Boot Bookworm
Complete the Customization

Release Contents

Latest Source Code Release Contents - Branches and Commit IDs

Component	Location	Branch	Tag/Commit ID
GHRD	https://github.com/ArrowElectronics/ghrd-socfpga	master	QPDS26.1_REL_GSRD_PR/a813239ce177133aeaae62a1f7b66860266addcd
Linux	https://github.com/ArrowElectronics/linux-socfpga	socfpga-6.18.2-lts	QPDS26.1_REL_GSRD_PR/232e81af478e344b8e0cdfcc4265f986a38ee4cc
U-Boot	https://github.com/ArrowElectronics/u-boot-socfpga	socfpga_v2026.01	QPDS26.1_REL_GSRD_PR/14eb3d155c2f57769e1e16a72f1551661a336c56
Arm Trusted Firmware	https://github.com/ArrowElectronics/arm-trusted-firmware	socfpga_v2.14.0	QPDS26.1_REL_GSRD_PR/4a4b4573e12fabd0a88e95952af49840db6b770d

Prerequisites

Host machine running Linux (for Quartus, ATF, U-Boot, Linux & Yocto). Ubuntu 22.04 was used, but other versions may work too. For Quartus only, optionally, a Host Machine running Windows.
Internet connection to download the tools and clone the repositories from github. If you are behind a firewall you will need your system administrator to enable you to get to the git trees.
Quartus Prime Pro version 26.1
Altera Video and Vision Processing (VVP) Suite License

Set up the Environment

Open a shell

    $ sudo rm -rf agilex_5
    $ mkdir agilex_5
    $ cd agilex_5
    $ export TOP_FOLDER=`pwd`

Download and setup the the toolchain as follows:

    $ cd $TOP_FOLDER
    $ wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
    $ tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
    $ rm -f gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
    $ export PATH=`pwd`/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu/bin:$PATH
    $ export ARCH=arm64
    $ export CROSS_COMPILE=aarch64-none-linux-gnu-

Build the Golden Hardware Reference Design

This can be built under Windows or Linux.

Open a shell (niosv command shell for Windows)

For Linux, specify the path to the Quartus installation

    $ export PATH="<path to >/altera_pro/26.1/quartus/bin:$PATH"

Clone the repository

    $ cd $TOP_FOLDER
    $ git clone -b QPDS26.1_REL_GSRD_PR https://github.com/ArrowElectronics/ghrd-socfpga ghrd-socfpga
    $ cd ghrd-socfpga/axe5_falcon_ghrd

Enable the Video Subsystem

    open the project in Platform Designer
    $ qsys-edit --quartus-project=axe5_falcon_top --1=ghrd_system.qsys

    check the 'Use' checkbox next to the video_subsystem
    enter the four hdmi signals in the export column. ensure it is exactly as shown in the snapshot below.

    Save and exit.
    $ File-->Save. Close. File-->Exit. No

Modify the Verilog and pin assignments files to include the video subsystem

    sed -i '30s|^//`define wHDMI|`define wHDMI|' sources/axe5_falcon_top.v
    sed -i '14s/^set wHDMI 0/set wHDMI 1/' sources/axe5_falcon_pin_assignment.tcl

Add pin assignments

    quartus_sh -t sources/axe5_falcon_top.tcl

Compile the Quartus project

    quartus_sh --flow compile axe5_falcon_top

The following file is created:

$TOP_FOLDER/ghrd-socfpga/axe5_falcon_ghrd/output_files/axe5_falcon_top.sof

Build Arm Trusted Firmware

    $ cd $TOP_FOLDER
    $ rm -rf arm-trusted-firmware
    $ git clone -b QPDS26.1_REL_GSRD_PR https://github.com/ArrowElectronics/arm-trusted-firmware arm-trusted-firmware
    $ cd arm-trusted-firmware
    $ make -j 48 PLAT=agilex5 bl31

The following file is created:

$TOP_FOLDER/arm-trusted-firmware/build/agilex5/release/bl31.bin (used for u-boot.itb generation)

Build u-boot

    $ cd $TOP_FOLDER 
    $ rm -rf u-boot-socfpga 
    $ git clone -b QPDS26.1_REL_GSRD_PR https://github.com/ArrowElectronics/u-boot-socfpga u-boot-socfpga 
    $ cd u-boot-socfpga

    enable dwarf4 debug info, for compatibility with arm ds
    $ sed -i 's/PLATFORM_CPPFLAGS += -D__ARM__/PLATFORM_CPPFLAGS += -D__ARM__ -gdwarf-4/g' arch/arm/config.mk

    only boot from SD, do not try QSPI and NAND
    $ sed -i 's/u-boot,spl-boot-order.*/u-boot\,spl-boot-order = \&mmc;/g' arch/arm/dts/socfpga_agilex5_axe5_falcon-u-boot.dtsi

    disable NAND in the device tree
    $ sed -i '/&nand {/!b;n;c\\tstatus = "disabled";' arch/arm/dts/socfpga_agilex5_axe5_falcon-u-boot.dtsi

    link to atf
    $ ln -s ../arm-trusted-firmware/build/agilex5/release/bl31.bin

    build U-Boot
    $ make clean && make mrproper
    $ make socfpga_agilex5_defconfig 

    use created custom configuration file to merge with the default configuration obtained in .config file. 
    $ ./scripts/kconfig/merge_config.sh -O . -m .config config-fragment-falcon
    $ make -j 64

The following files are created:

$TOP_FOLDER/u-boot-socfpga/u-boot.itb
$TOP_FOLDER/u-boot-socfpga/spl/u-boot-spl-dtb.hex

Build the Linux kernel

Download and compile Linux

    $ cd $TOP_FOLDER 
    $ rm -rf linux-socfpga
    $ git clone -b QPDS26.1_REL_GSRD_PR https://github.com/ArrowElectronics/linux-socfpga linux-socfpga 
    $ cd linux-socfpga

    add arrow dts folder as Makefile option 
    $ sed -i '$ a subdir-y += arrow' arch/arm64/boot/dts/Makefile

    $ make defconfig 
    use created custom configuration file to merge with the default configuration obtained in .config file.
    $ ./scripts/kconfig/merge_config.sh -O ./ ./.config ./config-fragment-falcon

    make oldconfig
    $ make -j 64 Image && make arrow/socfpga_agilex5_axe5_falcon.dtb

The following files are created:

$TOP_FOLDER/linux-socfpga/arch/arm64/boot/Image
$TOP_FOLDER/linux-socfpga/arch/arm64/boot/dts/arrow/socfpga_agilex5_axe5_falcon.dtb

Create an Integrated SOF file

This section presents how to add the FSBL to the SOF file which is the output of the hardware project compilation. This creates a new SOF file which can be used to configure the device through the Quartus Programmer. This is useful during development, as it takes much less time than writing a configuration image to QSPI.

Linux Environment

    $ export PATH="<path to >/altera_pro/26.1/quartus/bin:$PATH"
    $ cd $TOP_FOLDER/ghrd-socfpga/axe5_falcon_ghrd/output_files/
    $ quartus_pfg -c axe5_falcon_top.sof  axe5_falcon_top_hps.sof -o hps_path=$TOP_FOLDER/u-boot-socfpga/spl/u-boot-spl-dtb.hex

Windows Environment

    $ open a Nios V Command Shell
    $ cd <path to>/ghrd-socfpga/axe5_falcon_ghrd/output_files/
    $ copy u-boot-spl-dtb.hex from the linux host to the output_files directory
    $ quartus_pfg -c axe5_falcon_top.sof  axe5_falcon_top_hps.sof -o hps_path=u-boot-spl-dtb.hex

Create an Integrated JIC file

This section shows how to take the integrated sof file and create a jic file that can be programmed into the SDM QSPI flash. Note that downloading a sof file will not support the functionality of the linux reboot command or the HPS COLD RESET due to SDM requirements. It is useful to flash the QSPI when these functions are necessary.

Linux Environment

    $ export PATH="<path to >/altera_pro/26.1/quartus/bin64:$PATH"        
    $ cd $TOP_FOLDER/ghrd-socfpga/axe5_falcon_ghrd/output_files/
    $ quartus_pfg -c axe5_falcon_top.sof axe5_falcon_top.jic -o hps=on -o device=MT25QU256 -o flash_loader=A5EE013BB23BE6S -o hps_path=$TOP_FOLDER/u-boot-socfpga/spl/u-boot-spl-dtb.hex -o mode=ASX4

Windows Environment

    $ open a Nios V Command Shell
    $ cd <path to>/ghrd-socfpga/axe5_falcon_ghrd/output_files/
    $ copy u-boot-spl.ihex from linux host to the output_files directory
    $ quartus_pfg -c axe5_falcon_top.sof axe5_falcon_top.jic -o hps=on -o device=MT25QU256 -o flash_loader=A5EE013BB23BE6S -o hps_path=u-boot-spl-dtb.hex -o mode=ASX4

The following files are created:

$TOP_FOLDER/ghrd-socfpga/axe5_falcon_ghrd/output_files/axe5_falcon_top.hps.jic
$TOP_FOLDER/ghrd-socfpga/axe5_falcon_ghrd/output_files/axe5_falcon_top.core.rbf (rename it to ghrd.core.rbf)

Downloading via JTAG

The Agilex™ 5 device has two JTAG device IDs for the ARM SoC and FPGA, respectively. The Secure Device Manager will determine whether to expose one or both.

Determine the number of JTAG devices.

    $ jtagconfig

Two devices:

1) Arrow-USB-Blaster [ARA31601-TEI0004]
  4BA06477   ARM_CORESIGHT_SOC_600
  0364F0DD   A5E(C065BB32AR0|D065BB32AR0)

One device:

1) Arrow-USB-Blaster [ARA31601-TEI0004]
  0364F0DD   A5E(C065BB32AR0|D065BB32AR0)

Substitute @n below with @1 for one device and @2 for two devices.

Download the sof.

    $ quartus_pgm -c 1 -m jtag -o "p;axe5_falcon_top_hps.sof@n"

Flash the QSPI. Use the Intel Download cable when programming the AXE5-falcon board from a Linux environment.

    $ quartus_pgm -c 1 -m jtag -o "pvi;axe5_falcon_top.hps.jic@n"

Customize the Raspberry Pi Bookworm Distribution

Download the Raspberry Pi Bookworm Distribution

copy the following files to the FAT partition of the SD card.

$TOP_FOLDER/ghrd-socfpga/axe5_falcon_ghrd/output_files/ghrd.core.rbf
$TOP_FOLDER/u-boot-socfpga/u-boot.itb
$TOP_FOLDER/linux-socfpga/arch/arm64/boot/Image
$TOP_FOLDER/linux-socfpga/arch/arm64/boot/dts/arrow/socfpga_agilex5_axe5_falcon.dtb

Boot Bookworm

Configure the hardware as shown in the Quick Start section.

Flash $TOP_FOLDER/ghrd-socfpga/axe5_falcon_ghrd/output_files/axe5_falcon_top.hps.jic as described in Flash the FPGA configuration file

Connect to the HPS target terminal.

Run the demo

Complete the Customization

Bookworm requires the user to customize and complete the installation during the first boot session.

Ensure the AXE5-Falcon is connected to the internet. This will be used to complete the installation.

A username and password must be specified.

Expand the Linux file partition

It is useful to maximize the size of the ext4 partition. Using the host terminal or a shell on the AXE5-Falcon, do the following.

    $sudo raspi-config

Then perform the following operation.

    → Advanced Options → Expand Filesystem → reboot

Release Notes

Initial release

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Desktop Linux Falcon 26.1

Table of Contents

Quick Start Guide

Overview

Theory of Operation

Golden Hardware Reference Design (GHRD)

Configure the Board for the Demo

Assemble the Hardware

Flash the FPGA configuration file

Connect to the target terminal

Run the demo

Build Instructions

Release Contents

Latest Source Code Release Contents - Branches and Commit IDs

Prerequisites

Set up the Environment

Build the Golden Hardware Reference Design

Build Arm Trusted Firmware

Build u-boot

Build the Linux kernel

Create an Integrated SOF file

Linux Environment

Windows Environment

Create an Integrated JIC file

Linux Environment

Windows Environment

Downloading via JTAG

Customize the Raspberry Pi Bookworm Distribution

Boot Bookworm

Complete the Customization

Expand the Linux file partition

Release Notes

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