0.5.0b1
Pre-release
Pre-release
Towards a 0.5.0 release!
This is a pre-release, pending physical validation of the most recent set of example designs.
Summary of Major Changes
- Lots of internals refactoring
- Many new examples and library parts
- Shrink-multiply operation
- Better (but not perfect) buck and boost converter component
- Change default netlist mode to refdes + pathname-as-value
- Prefer lower e-series values for passives
- Eliminate @init_in_parent
- Stricter mypy typing, including override annotations
- Black formatting
- Migration to pyproject.toml
- More stable netlists (when the design changes), enforce netlist diffs in examples
- Compositional passive (instead of inherited passive)
- Eliminate Bundle construct, all Ports can contain sub-Ports
- .connected(...) on PassiveConnector
- Move pick-and-place rotation into HDL footprint defs (instead of the postprocessing script), for non-parts-table parts
- Sub-board infrastructure, connector-pair constructs, multi-board netlist generation
- Refactor microcontroller dev boards to use the sub-board wrapper infrastructure (instead of the prior bespoke complex inheritance hierarchies)
- Reorganize parts libraries into more meaningful modules
- footprint(...) pins can take tuples as keys
- Lots of renaming, the more common ones have deprecation aliases, the less common ones are just moved
- PyPI publishing workflow
- USB ESD diode moved into connector
Full Changelog: v0.2.0...0.5.0b1