Introduction

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Introduction

The DRISC-V architecture was developed as part of a monography project, using the original RISC I architecture as a foundation. It was later refactored and extended based on the official RISC-V specification.

The architecture and all its subcomponents are designed with a strong educational focus, serving as didactic material for future engineers. While its primary goal is to be a learning tool, the project also tries to resemble a commercial-grade processor as closely as possible. Although the current version lacks certain features expected in a fully-fledged commercial architecture, it provides a solid foundation that can be expanded in future updates.

To understand the inner workings of the architecture, this wiki first introduces key aspects of the RISC-V specification and outlines which features have been implemented. In the following chapters, you'll find detailed explanations of each available component and how they operate.

Instructions for running the complete simulation and testing programs are provided in the subsequent pages of the wiki.