program index
This list provides a comprehensive overview of the functionality of each program available for the simulations.
A simple program that runs in an infinite loop using the ja (Jump Absolute) instruction.
The program counter (PC) continuously loops back to address 4, and register x1 increments indefinitely.
This program tests the AUIPC instruction.
The first three digits of the first register (ra) should correspond to 0x004, and the remaining digits should reflect the immediate value added (0xf). Each subsequent register increments the value by 4 and modifies the immediate, resulting in the following values:
This program tests all branch instruction conditions. It first checks when the jump should be taken, then verifies when it should not.
All registers from ra to a2 should contain the value 0xffffffff. If any of them contain 0, the condition is not functioning correctly.
A program that tests the call and ret pseudo-instructions.
This program requires the CSR Controller to be enabled. It tests all available CSRs to verify proper functionality and ends with an mret instruction, which should change the privilege bit.
Register values may vary between Logisim and the SystemVerilog simulation due to differences in how the Real-Time Device is implemented.
This program checks for register or memory access hazards in the architecture. If the architecture is hazard-free, only registers tp and t0 should contain the value 0xffffffff.
This program tests whether the Load and Store instructions work correctly by loading different portions of the word 0xfafbfcfd and storing values at various memory addresses with different offsets. The program ends with a LUI instruction using the immediate 0xfffff. A variant called load skips the store instructions.
The load instructions should result in the following register values:
The store instructions should result in the following memory values:
This program tests all ALU operations.
It should produce the following register values. Note that in the current version of DRISC-V, division operations result in 0 and do not trigger an illegal instruction exception.
This program runs the QuickSort algorithm to sort an array of 16 bytes located immediately after the program.
The 16 bytes will be sorted. In Logisim, the result will be:
88 99 aa bb cc dd ee ff 00 11 22 33 44 55 66 77
In the SystemVerilog simulation, the array is different to demonstrate correct ASCII sorting. The result should be:
0123456789abcdef
This program runs the Insertion Sort algorithm to sort an array of 16 bytes located immediately after the program.
Same as the Quicksort program.
This program uses addi to set every register to 1.
This program copies a picture of a cat from RAM to the screen. It is larger than other programs, and in the SystemVerilog simulation, the program size must be increased for it to work.
This program tests terminal functionality.
The terminal should print:
This is a test string !@$%¨&*()_{}[]
The trap handler manages exceptions during program execution. When triggered, it prints the reason for the exception. Interrupts are not yet handled but can be implemented by adding a program after the interrupt labels in the assembly code. After printing the exception, the handler returns to the calling program.
Unlike other programs, the trap handler should be placed in its designated memory at address 0x80000000.
The trap caller generates exceptions to invoke the trap handler. It is user-controlled via keyboard input. When the program starts, typing 0, 2, 3, 4, 6, 8, or b will generate specific messages. Any other input will trigger an "unknown exception" error.
A separate program, Trap Handler Test, allows testing the trap handler without a CSR Controller. It should be used like a normal program to verify message output.
This program tests both the screen and keyboard input. It uses macros and assembler features to minimize code size.
A dot appears at the center of the screen and begins moving. The user can control its direction using the W, A, S, and D keys. Pressing Q stops the program.
