Main Internal Components

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Introduction

The DRISC-V architecture is composed of six internal components: the ALU, the Register File, the Program Counter, the Input Buffer, the Operation Controller, and the CSR Controller.

The DRISC-V architecture comprises six internal components: the ALU, the Register File, the Program Counter, the Input Buffer, the Operation Controller, and the CSR Controller.

These components communicate through five internal buses. The A, B, and C buses provide direct access to the Register File (A and B are used for reading register values, while C is used for writing results back). The Immediate Bus supplies the 32-bit immediate value extracted from the current instruction. Lastly, the Program Counter Bus carries the current instruction address from the Program Counter.

There are also two buses used for external communication: the IO Bus, used for data transfers, and the Address Bus, which provides the current address being used. The IO Bus connects with the B bus and the Input Buffer. The current address can indicate either the address of the current instruction or the address used in load and store instructions.

The following tabe gives a summary of all the busses and which components they are connected to.

Bus Connections Overview

Bus Name	Sources	Destinations
A Bus	Register File	ALU, Program Counter, Operation Controller, CSR Controller
B Bus	Register File	ALU, IO Bus
C Bus	ALU, Input Buffer, Program Counter, Immediate Bus, CSR Controller	Register File
Immediate Bus	Operation Controller	ALU, C Bus
Program Counter Bus	Program Counter	ALU, CSR Controller
IO Bus	External Devices, B Bus	External Devices, Operation Controller, Input Buffer
Address Bus	Program Counter	External Devices

The following image shows a simplified diagram of all internal components, along with their bus connections.

Note: There are short buses connecting the CSR Controller to both the Operation Controller and the Program Counter. These have been omitted from the diagram as they are highly specialized and not part of the general data flow.

Both simulations have been configured so that the CSR Controller can be easily removed. This allows for a simpler system configuration and disables the U, Zicsr, and Zicntr extensions.

Timing and Pipeline

The DRISC-V is a pipelined architecture, meaning multiple steps of each instruction processing are executed in parallel. It uses a 3-cycle pipeline, with each cycle divided into 2 phases. Below is an enhanced representation of the pipeline stages:

Cycle	Phase 1	Phase 2
1	Instruction Fetch (IF)	Instruction Decode (ID)
2	Execute (EX)	Memory Access or Register Write (MEM/WB)
3	Register Write from Load (WB)	—

The double phase allows the pipeline to operate using a single bus to transfer instructions and data from outside the data bus. For example, while the first phase is used to fetch the instruction from memory, the second phase allows the same bus to receive or send data to memory during load and store instructions.

Additionally, since data needs to be fetched from memory in load instructions during the second phase of the pipeline, and only then is the valid size (byte, short, word, signed/unsigned) calculated, the load instruction requires an extra cycle to write back the loaded value into the registers.

Below is an example of pipeline execution over time. Note that there is no need to insert bubbles to prevent hazards. However, after any jump instruction (JAL, JALR, Branch, MRET or System Trap), the instruction that would have been executed next is flushed and does not proceed through the pipeline.

Time	1	2	3	4	5	6	7	8
OP	IF-ID	EX-WB	—
Load		IF-ID	EX-MEM	WB-__
OP			IF-ID	EX-WB	—
Jump				IF-ID	EX-MEM	—
OP					IF-ID	—	—
Store						IF-ID	EX-MEM	—

The processor also contains a small component that was not previously mentioned: the Phase Controller. It consists of a simple flip-flop that toggles its value every clock cycle. The regular output is used to signal Phase 1, while the negated output represents Phase 2.