v1.1.2

What's Changed

• Updated README

Full Changelog: v1.0.2...v1.1.2

v1.1.1

Version 1.1.1

This release bundles a critical bug fix and the first suite of automated tests to improve the stability and maintainability of the processor simulator:

• Logging bug fix
  Resolved an issue where log entries were not being written to the log file as expected. [PR #35](#35).
  Full changelog (v1.0.0 → v1.1.0):
  v1.0.0...v1.1.0

• Automated tests added
  Introduced a suite of unit tests covering core functionality of the simulator, laying the groundwork for future test-driven development. [PR #39](#39).
  Full changelog (v1.0.2 → v1.1.1):
  v1.0.2...v1.1.1

v1.0.2

📦 Version 1.0.2 – Printing Cleanup & Documentation Update

Release Date: [Insert date]

🔧 What's Changed

• Cleaned up residual debug statements for a cleaner runtime output.
• Updated documentation to reflect logging practices and remove outdated references.

This release focuses on internal maintenance and documentation clarity, ensuring the simulator output remains clean and the project stays developer-friendly.

Full Changelog: [v1.0.1...v1.0.2](v1.0.1...v1.0.2)

v1.0.1

📦 Version 1.0.1 – ISA Logic Fixes

Release Date: [Pending release date]
Course: CSEN B501 – Computer System Architecture
Institution: German International University Berlin
Instructor: Dr. Hazem Ahmed

🛠️ Bug Fixes

• Corrected logical flaws in the Instruction Set Architecture (ISA) implementation.
• Ensured that each of the 12 supported instructions (R, I, and J types) now adheres strictly to the defined operational behavior as per the project specification.
• Improved handling of edge cases in instructions involving memory access and control flow.

✅ Stability

• This is a minor patch release addressing functional correctness without modifying the overall architecture or execution flow.

🔁 Upgrade Notes

• This version is backward-compatible with v1.0.0 test programs.
• All debugging and output formats remain unchanged.

v1.0.0

📦 Version 1.0.0 – Initial Stable Release

Release Date: May 23, 2025
Course: CSEN B501 – Computer System Architecture
Institution: German International University Berlin
Instructor: Dr. Hazem Ahmed

🚀 Overview

Version 1.0.0 represents the first complete and stable implementation of a C-based simulator for a fictional processor design based on the Von Neumann architecture. This release complies fully with the project specification outlined in the Spring 2025 semester, including memory structure, instruction decoding, pipelining, and execution flow.

🧠 Features Implemented

• Memory Architecture

  • 2048×32-bit main memory (word-addressable)
  • Program instructions in addresses 0–1023, data in 1024–2047
  • 33 registers including 31 GPRs, PC, and zero register

• Instruction Set

  • 12-instruction custom ISA (R, I, J types)
  • Full support for arithmetic, logical, branching, and memory access operations

• Datapath and Pipelining

  • 5-stage datapath: IF, ID, EX, MEM, WB
  • Simulated pipeline supporting up to 4 instructions in parallel
  • Pipeline behavior synchronized with memory access constraints
  • Execution timing logic based on 7 + (n–1)×2 formula

• Execution Model

  • Full clock-cycle simulation with register/memory tracking
  • Logging of instruction activity at each stage per clock cycle
  • Final memory and register dump after execution completion

🧪 Testing and Output

• Handles a wide variety of test programs using the full instruction set
• Logs clock cycle progress, instruction flow, register/memory updates
• Console output confirms correct stage-wise execution and updates

📁 Contents

• *.c source files for simulator and logic
• Instruction parsing and execution pipeline
• Test assembly input files