v1.0.0

📦 Version 1.0.0 – Initial Stable Release

Release Date: May 23, 2025
Course: CSEN B501 – Computer System Architecture
Institution: German International University Berlin
Instructor: Dr. Hazem Ahmed

🚀 Overview

Version 1.0.0 represents the first complete and stable implementation of a C-based simulator for a fictional processor design based on the Von Neumann architecture. This release complies fully with the project specification outlined in the Spring 2025 semester, including memory structure, instruction decoding, pipelining, and execution flow.

🧠 Features Implemented

• Memory Architecture

  • 2048×32-bit main memory (word-addressable)
  • Program instructions in addresses 0–1023, data in 1024–2047
  • 33 registers including 31 GPRs, PC, and zero register

• Instruction Set

  • 12-instruction custom ISA (R, I, J types)
  • Full support for arithmetic, logical, branching, and memory access operations

• Datapath and Pipelining

  • 5-stage datapath: IF, ID, EX, MEM, WB
  • Simulated pipeline supporting up to 4 instructions in parallel
  • Pipeline behavior synchronized with memory access constraints
  • Execution timing logic based on 7 + (n–1)×2 formula

• Execution Model

  • Full clock-cycle simulation with register/memory tracking
  • Logging of instruction activity at each stage per clock cycle
  • Final memory and register dump after execution completion

🧪 Testing and Output

• Handles a wide variety of test programs using the full instruction set
• Logs clock cycle progress, instruction flow, register/memory updates
• Console output confirms correct stage-wise execution and updates

📁 Contents

• *.c source files for simulator and logic
• Instruction parsing and execution pipeline
• Test assembly input files