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v0.2 - Exceptions and Interrupts

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@HalfTimeOfLife HalfTimeOfLife released this 20 Sep 14:18
· 3 commits to master since this release
v0.2
6d4de70

Exception handling and interrupt controller support for the AArch64 bare-metal kernel.

Added

  • src/exceptions/vectors.s: AArch64 exception vector table, 16 entries, 2 KB aligned, synchronous and IRQ handler entries (VBAR_EL1 + 0x200 / + 0x280), 14 unused stubs
  • src/exceptions/handlers.s: synchronous handler (dumps ELR_EL1/SPSR_EL1/ESR_EL1), IRQ handler (dumps GICC_IAR), both returning via eret
  • src/gic/gic.s, src/gic/gic.inc: GICv2 driver (gic_init), Distributor and CPU interface setup
  • src/uart/uart.s: uart_put_hex, prints a 64-bit register value in hexadecimal
  • VBAR_EL1 configured and GIC initialized in _start, before any code that could trigger an exception
  • notes/v02.md: full theory and implementation walkthrough (AArch64 exception model, GICv2 architecture, register reference)

Verification

The kernel successfully boots on QEMU virt, triggers a deliberate svc #0 (EC=0x15 in ESR_EL1) and a self-targeted SGI 0 via GICD_SGIR, both correctly routed, handled, and returned from:

Hello, AArch64!

Synchronous exception caught!
ELR_EL1:  0x0000000040000024
SPSR_EL1: 0x0000000040000345
ESR_EL1:  0x0000000056000000

IRQ exception caught!

GICC_IAR: 0x0000000000000000
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