v0.3 - ARM Timer

Periodic timer interrupts for the AArch64 bare-metal kernel, built on the GICv2 support introduced in v0.2.

Added

• src/timer/timer.s: timer_init/timer_set_interval, configures the non-secure EL1 physical timer (CNTP_TVAL_EL0/CNTP_CTL_EL0) for a ~100 Hz tick
• src/gic/gic.s: gic_init extended to enable the timer's PPI (GIC ID 30, confirmed via QEMU's device tree) alongside the existing SGI
• src/exceptions/handlers.s: el_irq now dispatches by interrupt ID between the SGI test and the timer; timer_irq re-arms the one-shot timer on every interrupt and tracks a running tick_count
• notes/v03.md: full theory and implementation walkthrough (ARM generic timer architecture, PPI ID derivation from the device tree, register reference)

Verification

The kernel boots on QEMU virt, runs through the existing svc/SGI tests from v0.2, then the timer fires periodically and tick_count is printed every 512 ticks:

Tick: 0x0000000000000200
Tick: 0x0000000000000400
Tick: 0x0000000000000600
Tick: 0x0000000000000800

Each value increases by exactly 512, confirming the timer re-arms and fires correctly on every interrupt.

v0.2 - Exceptions and Interrupts

Exception handling and interrupt controller support for the AArch64 bare-metal kernel.

Added

• src/exceptions/vectors.s: AArch64 exception vector table, 16 entries, 2 KB aligned, synchronous and IRQ handler entries (VBAR_EL1 + 0x200 / + 0x280), 14 unused stubs
• src/exceptions/handlers.s: synchronous handler (dumps ELR_EL1/SPSR_EL1/ESR_EL1), IRQ handler (dumps GICC_IAR), both returning via eret
• src/gic/gic.s, src/gic/gic.inc: GICv2 driver (gic_init), Distributor and CPU interface setup
• src/uart/uart.s: uart_put_hex, prints a 64-bit register value in hexadecimal
• VBAR_EL1 configured and GIC initialized in _start, before any code that could trigger an exception
• notes/v02.md: full theory and implementation walkthrough (AArch64 exception model, GICv2 architecture, register reference)

Verification

The kernel successfully boots on QEMU virt, triggers a deliberate svc #0 (EC=0x15 in ESR_EL1) and a self-targeted SGI 0 via GICD_SGIR, both correctly routed, handled, and returned from:

Hello, AArch64!

Synchronous exception caught!
ELR_EL1:  0x0000000040000024
SPSR_EL1: 0x0000000040000345
ESR_EL1:  0x0000000056000000

IRQ exception caught!

GICC_IAR: 0x0000000000000000

v0.1 - Minimal boot and UART output

First release of the AArch64 bare-metal kernel.

Added

• linker.ld: custom linker script, kernel linked at 0x40000000, stack layout with _stack_bottom and _stack_top
• src/boot/boot.s: AArch64 bare-metal boot code, stack initialization and kernel halt loop
• src/uart/uart.s: UART MMIO driver for QEMU virt, uart_putc and uart_puts, null-terminated string output, UART transmit FIFO polling through UART_FR, character output through UART_DR
• Makefile: assembly and linking of the kernel, automatic generation of the build/ directory and object files
• scripts/check_setup.sh: development environment verification
• build/: generated object files and kernel ELF
• AArch64 assembly-only implementation with no C runtime or standard library

Verification

The kernel successfully boots on QEMU virt and outputs:

Hello, AArch64!